I refer Vybrid RM of Table 9-6. Synchronous Mode.
There are 4settings are described..
Is this the 4 settings example?
Do Will Do not the other settings?
I need to the connect to I2C rating of the destination will need to the IPG below 20MHz.
For example,Theparameter set is PLL1-> PFD3 (396MHz), ARM_DIV = 1, BUS_DIV = 5, IPG_DIV = 4 ,will be IPG = 19.8MHz
But this settings not stated in Table 9-6.
Do the above setting is possible?
For the use of there is no parameter set forth in Table 9-6, or there is no concern?
Solved! Go to Solution.
Synchronous setting requires that the platform clock (usually 133-166MHz) have to be half of SDRAM clock.
So first line in table is not correct (it should be deleted in next RM revision.)
Synchronous mode is important only when is used SDRAM. If you not using SDRAM then you can use default asynchronous mode.
For I2C clock is important peripheral clock (IPS bus clock). It can be divided by CCM_CACRR [IPG_CLK_DIV]
So if you need 20MHz then platform would have to be 80MHz only and CA5 and SDRAM 160MHz. This we degrade performance significantly.
If not used SDRAM than you can divide also platform clock.
But why you need just low IPS bus clock? I2C CLOCK divider can be set up to 15360 using MUL and divider.
I have checked the documetation and those are just examples of clock settings.
But you can for sure set the IPG_CLK_DIV to 4, BUS_DIV to 5 too. This means that you can set the IPG clock below 20MHz.
I hope that helps,