Vybrid RD_DL_SET

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Vybrid RD_DL_SET

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sugiyamatoshihi
Contributor V

Hi,

We tested memory timing DDR validation tool.

We heard we can use fixed value for RD_DL_SET=4 and GATE_CFG=0 regardless of the result of DDR validation results.

However, the result of RD_DL_SET shows good values are 4,5,6,7. It should use 5 or 6 for RD_DL_SET. Do you recommend still use 4 regardress this results?

Best Regards,

Sugiyama

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Sugiyama,

Mark is definitely the right person to ask advice on this but in case it helps, my two cents:

RD_DL_SET at 4 should work on most normal operations but you may increase the delay if necessary. In this case since the tool validated 4,5,6 and 7 you should be able to use 4 without problems. Increasing further than fours should not be necessary but you may do so to have a more robust implementation, although 4 will suffice.

Regards,

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Sugiyama,

Mark is definitely the right person to ask advice on this but in case it helps, my two cents:

RD_DL_SET at 4 should work on most normal operations but you may increase the delay if necessary. In this case since the tool validated 4,5,6 and 7 you should be able to use 4 without problems. Increasing further than fours should not be necessary but you may do so to have a more robust implementation, although 4 will suffice.

Regards,

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sugiyamatoshihi
Contributor V

Hi, Gusarambula,

Thanks for your answer.

I will communicate with customer.

Best Regards,

Sugiyama

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sugiyamatoshihi
Contributor V

@Mark Middleton

Hi, Mark,

Could you  advice the value of RD_DL_SET?

Best Regards,

Sugiyama

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TheAdmiral
NXP Employee
NXP Employee

Hi Sugiyama-san,

The RD_DL_SET field is the amount of clock cycles that the PHY waits after it sends the Read Command to the DDR plus the Read Latency value, before it notifies the controller that data is read in the READ FIFOs to be passed to the controller. Stated another way: After the programmed number Read Latency clocks, the DDR will strobe out the first data byte on the data lane. The PHY will begin counting from that point the number of clock cycles programmed into RD_DL_SET, and then notify the controller that data in the READ FIFOs is valid.

The setting of RD_DL_SET accounts for all timing necessary to:

1) Transfer data from the DDR to the processor over the PCB,

2) Transfer data from the pins of the processor to the input of the READ FIFO.

3) The one-quarter clock phase shift of the DQS strobe to clock the DQ values into the FIFO

4) And any timing difference between the Controller clock domain and the PHY domain.

Also note that the controller is sent the data from both the rising edge and falling edge of the DQS strobe at the same time, and that data is transferred across the DFI bridge only on the rising edge of the master clock.

On most boards, a setting of 0x4 is all that is required. On PCB with much longer PCB traces, a setting of 0x5 may be neccessary to avoid problems. We currently recommend 0x5 as a settings just to keep customers from complaining. The net effect of adding clock cycles to RD_DL_SET is just adding latency to a Read operation, thus reducing throughput.

Hope this answers your question for you,

Mark

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sugiyamatoshihi
Contributor V

Hi, Mark,

Thank you for explanation.

I understood the parameter of RD_DL_SET.  This is very helpful to explain it.

Thanks you very much.

Sugiymama

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