T1040 DDR3 PCB Routing

[mohsenhaghighat]

Hello,

we design a board with T1022 processor, In this board we use DDR3 SDRAM chip(not DIMM). When we want to design the PCB of the board, we do not find good information about DDR3 PCB topology.

can anybody help where we can find it?

I know that in DDR3 topology we must use fly by topology, But we do not know anything about its data and address timing.

where we can find good information about T10xx DDR3 PCB routing and PCB topology?

thanks

[r8070z]

Have a great day,

There is application note Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces
http://www.nxp.com/files/32bit/doc/app_note/AN3940.pdf 

It is recommended using topology like the DDR3 memory module topologies. Both DIMM and SO-DIMM modules fundamentally utilize the same “flyby” topology. See for example

http://subscriptions.amd.com/assets/pdf/zen_memory_whitepaper_final.pdf 

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[mohsenhaghighat]

Thanks Serguri. This app.note does not have good information for Discrete DDR3 chips and In this app.not, The length and width of Data track, Address track and clock track do not Determinate properly for Discrete chips.

Another Question,Does T1022 DDR3L must use "FLY BY" architecture?

[r8070z]

What do you mean “the length and width of Data track, Address track and clock track do not determinate properly for Discrete chips”? What is specific for discrete chips? The AN3940 is for discrete memory chips too. When item 21 says that “length for data/address/command signals are no longer than 7 inches” or item 27 says “ensure that all the data lanes are matched to within 2.0 inches” they mean length to the memory chip pin. Item 32 says directly "the clock signal trace length from the memory controller to any given DDR3 chip must be longer than its corresponding strobe trace length." These requirements must be satisfied in any topology. DDR3L is a DDR3 memory which can operate at 1.35V instead of 1.5V. The flyby topology is recommended due to the best signal integrity.