some question about s32k144'LPSPI

[annqian]

void LPSPIx_init_master(LPSPI_Type *LDSPIx)
{
 if(LDSPIx == LPSPI0)
 {
   PCC->PCCn[PCC_LPSPI0_INDEX] = 0;          /* Disable clocks to modify PCS ( default) */
      PCC->PCCn[PCC_LPSPI0_INDEX] = 0xC6000000; /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */
 }else if(LDSPIx == LPSPI1)
 {
   PCC->PCCn[PCC_LPSPI1_INDEX] = 0;          /* Disable clocks to modify PCS ( default) */
   PCC->PCCn[PCC_LPSPI1_INDEX] = 0xC6000000; /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */
 }
 else
 {
   PCC->PCCn[PCC_LPSPI2_INDEX] = 0;          /* Disable clocks to modify PCS ( default) */
   PCC->PCCn[PCC_LPSPI2_INDEX] = 0xC6000000; /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */
 }

  LDSPIx->CR    = 0x00000302;   /* reset module for configuration */
  LDSPIx->CR    = 0x00000000;   /* Disable module for configuration */
  LDSPIx->IER   = 0x00000000;   /* Interrupts not used */
  LDSPIx->DER   = 0x00000000;   /* DMA not used */
  LDSPIx->CFGR0 = 0x00000000;   /* Defaults: */
        /* RDM0=0: rec'd data to FIFO as normal */
        /* CIRFIFO=0; Circular FIFO is disabled */
        /* HRSEL, HRPOL, HREN=0: Host request disabled */
  LDSPIx->CFGR1 = 0x00000001;   /* Configurations: master mode*/
        /* PCSCFG=1: PCS[3:2] are disenabled */
        /* OUTCFG=0: Output data retains last value when CS negated */
        /* PINCFG=0: SIN is input, SOUT is output */
        /* MATCFG=0: Match disabled */
        /* PCSPOL=0: PCS is active low */
        /* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */
        /* AUTOPCS=0: does not apply for master mode */
        /* SAMPLE=0: input data sampled on SCK edge */
        /* MASTER=1: Master mode */
  LDSPIx->TCR   = 0x10000007;   /* Transmit cmd: PCS3, 16 bits, prescale func'l clk by 4, etc*/
        /* CPOL=0: SCK inactive state is low */
        /* CPHA=0: Change data on SCK lead'g, capture on trail'g edge*/
        /* PRESCALE=2: Functional clock divided by 2**2 = 4 */
        /* PCS=0: Transfer using PCS0   !!!!!!!!!!!!!*/
        /* LSBF=0: Data is transfered MSB first */
        /* BYSW=0: Byte swap disabled */
        /* CONT, CONTC=0: Continuous transfer disabled */
        /* RXMSK=0: Normal transfer: rx data stored in rx FIFO */
        /* TXMSK=0: Normal transfer: data loaded from tx FIFO */
        /* WIDTH=0: Single bit transfer */
        /* FRAMESZ=7: # bits in frame = 7+1=8 */
  LDSPIx->CCR   = 0x04090812;   /* Clock dividers based on prescaled func'l clk of 100 nsec */
        /* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */
        /* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) */
        /* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */
        /* SCKDIV=18: SCK divider =18+2 = 20 (1 usec: 0.5 MHz baud rate) *///spi_clk=500khz
  LDSPIx->FCR   = 0x00000002;   /* RXWATER=0: Rx flags set when Rx FIFO >0 */
        /* TXWATER=2: Tx flags set when Tx FIFO <= 3 */
  LDSPIx->CR    = 0x00000009;   /* Enable module for operation */
        /* DBGEN=1: module enabled in debug mode */
        /* DOZEN=0: module enabled in Doze mode */
        /* RST=0: Master logic not reset */
        /* MEN=1: Module is enabled */
}

void SPI_init (void) {

//SPI flash
#if SPI0
 PORTD->PCR[15] |=PORT_PCR_MUX(4);//LPSPI0_SCK  CLK
 PORTD->PCR[16] |=PORT_PCR_MUX(4);//LPSPI0_SIN  MISO
 PORTB->PCR[1] |=PORT_PCR_MUX(3);//LPSPI0_SOUT MOSI
 PORTB->PCR[0] |=PORT_PCR_MUX(3);//LPSPI0_PCS0 CS
    //OTHER GPIO SETING
  Gpio_Set_Do_TE(PORT_GPIOD, 13, DO_MODE_PP);//RST LOW RESET

  Gpio_Set_Do_TE(PORT_GPIOD, 14, DO_MODE_PP);//SOF NOT USE

  Gpio_Set_Di_TE(PORT_GPIOD, 12, DI_MODE_NUPULL);//INT
#endif

}

uint8_t SPI_TX[20], SPI_RX[20];
void SPI_WR(uint8_t len)
{
 uint8_t i = 0;

    for(i=0; i<len; i++)
    {
      while((LPSPI0->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);//sr=0x01
                                         /* Wait for Tx FIFO available */
      LPSPI0->TDR = SPI_TX[i];//sr=0x703  fsr=0x10000
  // while((LPSPI0->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
             /* Wait at least one RxFIFO entry */
   SPI_RX[i]= LPSPI0->RDR;            /* Read received data */
   LPSPI0->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */
   LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */

    }
}

use LPSPI0 , SPI_WR ()funciton  read and write many byte one time.but SPI_RX[] is always 0xFF. pin of CLK,CS and SOUT

has a sigal. SIN always high.

 while((LPSPI0->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);  cannot pass even as SR.RDF ==1.

can you help me?

Thanks!

[PetrS]

Hi,

I have tested your code on the EVB and it works fine, I think. I see 20 8-bit frames on SPI0. If the SIN pin is not connected 0xFF is received for each frame. 

The code passed  while((LPSPI0->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0); statement normally.

Only I see in your code you did not enable clock for PORTD, but maybe you did it somewhere else.

PCC->PCCn[PCC_PORTD_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTD */

BR, Petr

[annqian]

Hi,

   the clock of PORTD is enable in other function ,and I have figure out the problem.but  thank you anyway.