I'm trying to figure out the S32k14x PLL frequency tolerance, I found in the data sheet the following table that specify the lock exit frequency tolerance Dunl value. I'm a little bit confused if this value represent the PLL frequency tolerance. if no where i can find this info?
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Hello,
The table specifies typ. PLL Jitter over one PLL period and accumulated jitter over 1us.
BR, Daniel
it seems the accuracy is kind of high. say Fvco_clk =320M, the period is 3.125ns, so the tolerance is 75ps/3.125ns=2.4%.
but I do not know whether the calculation method is right or not. maybe there exists other calculation method I do not know.
do you have any ideas?
Hello,
The table specifies typ. PLL Jitter over one PLL period and accumulated jitter over 1us.
BR, Daniel
Hi, Daniel
Could you please show how to calculate the accuracy of PLL? let's say Fvco_clk=320MHz. could you show the detailed calculation?
is the calculation right or not: 75ps/(1000/320ns)=2.4% ?
I also have to calculate UART baudrate(20kbps) accuracy, which is derived from SPLL_CLK.
Daniel,
I have the same question about the PLL Lock Exit Frequency Tolerance. If we are trying to quantify the overall PLL timing error say over a 1uS period, is the long term jitter all that we consider? Does the PLL Lock Exit Frequency Tolerance have any bearing on the timing error in this case?