s32k14x PLL Frequency Tolerance

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

s32k14x PLL Frequency Tolerance

Jump to solution
2,753 Views
Mimo88
Contributor I

I'm trying to figure out the S32k14x PLL frequency tolerance, I found in the data sheet the following table that specify the lock exit frequency tolerance Dunl value. I'm a little bit confused if this value represent the PLL frequency tolerance. if no where i can find this info?

Mimo88_0-1602774194085.png

 

0 Kudos
1 Solution
2,741 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hello,

The table specifies typ. PLL Jitter over one PLL period and accumulated jitter over 1us.

 

BR, Daniel

View solution in original post

0 Kudos
4 Replies
2,444 Views
aceangle
Contributor II

it seems the accuracy is kind of high. say  Fvco_clk =320M, the period is 3.125ns, so the tolerance is 75ps/3.125ns=2.4%.

but I do not know whether the calculation method is right or not.  maybe there exists other calculation method I do not know.

do you have any ideas?

0 Kudos
2,742 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hello,

The table specifies typ. PLL Jitter over one PLL period and accumulated jitter over 1us.

 

BR, Daniel

0 Kudos
2,444 Views
aceangle
Contributor II

Hi, Daniel

Could you please show how to calculate the accuracy of PLL? let's say Fvco_clk=320MHz. could you show the detailed calculation?

is the calculation right or not: 75ps/(1000/320ns)=2.4% ?

I also have to calculate UART baudrate(20kbps) accuracy, which is derived from SPLL_CLK.

aceangle_1-1636083869631.png

aceangle_0-1636084000145.png

 

 

 

0 Kudos
2,665 Views
gobrien8
Contributor I

Daniel, 

I have the same question about the PLL Lock Exit Frequency Tolerance.  If we are trying to quantify the overall PLL timing error say over a 1uS period, is the long term jitter all that we consider?  Does the PLL Lock Exit Frequency Tolerance have any bearing on the timing error in this case? 

0 Kudos