Why does s32k144 take more time to run code in ram?

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Why does s32k144 take more time to run code in ram?

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中当陈
Contributor III

Hello!

I have a problem. I test some codes, When s32k144 runs these codes in ram, It takes more time. And when s32k144 runs code in flash, It take less time.In my opinion, the result must be reversed. So I am confused。

My IDE: WIN10_64 + IAR 7.60.2 for ARM

And my codes are these:

pastedImage_11.png

delay() function returns the executive time of "while(count  >  0)". And then the array "time" stores the executive time. delayTest() function calls delay() function continuously。

example 1:

The codes of delay() function  are in flash. And the codes of delayTest() function are in flash.

the average value of the array time is 2820.

example 2:

The codes of delay() function are in ram. And the codes of delayTest() function are in flash.

the average value of the array time is 3220.

example 3:

The codes of delay() function are in flash. And the codes of delayTest() function are in ram.

the average value of the array time is 3700.

 

I hope someone could help me.

Best regards to you!

Thanks!

4 Replies

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello,

Which SRAM region do you use?

You should get the best results when you use SRAM_L for code and SRAM_U for data.

Please see below.

pastedImage_1.png

pastedImage_2.png

Regards,

Daniel

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1,313 Views
中当陈
Contributor III

Hi, Daniel

Thank you for you reply. It's very useful to me.

I place the delay() function and delayTest() function in SRAM_U. Then I will test these functions in SRAM_L.

And I place global variable in SRAM_L. So the access efficiency of data in SRAM_L will be lower than the access efficiency of data in SRAM_U?

Best Regards

Chen

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Chen,
The core has zero-wait-state access to both instructions and data in SRAM_L region via Processor Code (PC) bus.
But as the bus name imply, normal operation has code accesses on the PC bus and data accesses on the Processor System (PS) bus (Section 33.2.1, RM rev.8).
This allows simultaneous core accesses to both instructions and data and provides better performance.

Regards,
Daniel

1,313 Views
中当陈
Contributor III

Hi Daniel,

Thank you for your reply!  Last week, I was on vacation。I am sorry for my late reply.

Your answer solves my problem! Now I know how to redesign my programs.

Thanks again!

Best Regards!

Chen

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