What is the value that can be set in the SCG_VCCR register on the S32K144?

[Hozumi]

What is the value that can be set in the SCG_VCCR register on the S32K144?

Only Slow IRC can be set in the SCS field.

Is there a choice that can be set in the DIVCORE field?

The default value is 3 (Divide-by-4).

There is a statement that this can be changed in OPBYTE, but there is no description of DIVCORE in the description of OPBYTE.

Is it possible to change with Write?

Are there any restrictions regarding DIVCORE and also DIVBUS and DIVSLOW?

After setting 0x02070000 to SCG_VCCR, the SCS field of the SCG_CSR register is monitored, but it cannot be changed to 2 (Slow IRC).

[danielmartynek]

Hello Kensuke,

As you can see below, SIRC can be used only in VLPR.

All the other clock sources must be disabled.

The description of SCG_VCCR[COREDIV] seems to be incorrect.

As you mentioned, the default value is 0x3 (div-by-4) and there is no option to changed it in the FOPT byte but by a 32b write to the VCCR register only.

Let me report that.

The frequency is restricted.

DS rev.13:

Section 5.8 Device clock specifications

RM rev.12.1:

Table 27-7. Very low power RUN example

Section 27.4.3 VLPR mode clocking

The SCG_CSR reflects the configuration set by SCG_VCCR only when the MCU is in the VLPR mode (SMC_PMSTAT[PMSTAT] == 0x4).

Regards,

Daniel

[danielmartynek]

Hello Kensuke,

The incorrect description of SCG_VCCR[COREDIV] has been reported and it will be changed.

The COREDIV value is not loaded from the flash, default value is 0x3 (div-by-4).

Regards,

Daniel