The S32K312 DMA + IDLE fails to receive data.

[li3]

Hi NXP,

S32K312 I use DMA to receive data and promise to receive data in Buffer in IDLE interrupt callback function. When the program runs and the first IDLE interrupt occurs, the receiving Buffer can receive data and print it, but the second time to send data, the receiving Buffer does not receive data.

If I don't print in IDLE interrupt callback receive the data in Buffeer. In Debug mode, you can see that data is normally received in the receiving Buffer.

Please help me solve this problem in conjunction with my project. thank you.

Best  Regards,
Li 3

[li3]

Why uint8_t uartrxBuffer[256]; Put it in ".mcal_bss_no_cacheable" and it'll work, okay? Please explain the reason. Thank you.

[danielmartynek]

Hi @li3,

If the DMA writes to the buffer, you have no guarantee whether the data the core reads is from the buffer in sram or from the cache. The buffer must be either in a non-cacheable sram, or you would need to invalidate the cache each time before the core reads it.

Regards,

Daniel

[li3]

Hi Daniel，

Thanks for your reply, I understand what you mean. If RXbuffer is in non-cacheable sram, the cache should be invalidated before each read, if not, it will only affect the read operation.

But after I read the RXbuffer, why can't I write data to the RXbuffer using DMA? I don't understand the connection. Please elaborate. Thank you.

Best  Regards,
Li 3

[danielmartynek]

The DMA can write to the buffer, but the core does not see the data in the buffer written by the DMA, because it reads the cache instead.

BR, Daniel

[li3]

Hi Daniel，

The rxbuffer I write is a receive array that I define. I used debug mode to view the data stored in the rxbuffer and found that after printing the data in the rxbuffer, DMA cannot receive the data sent by the PC, while rxbuffer still has the previous data. Why is this?

Combined with my above project, answer it, thank you.

Best  Regards,
Li 3

[danielmartynek]

HI @li3,

If I'm not mistaken, you have already confirmed that it works when the buffer is in a non-cacheable memory.

This is the expected behavior of the cache.

Regards,

Daniel

[li3]

Hi Daniel，

Yes, this receive array goes into non-cacheable memory and receives fine.

I want to know that I put the receive array into the cacheable memory, do a print or copy of the data in the receive array, and find that DMA can not receive data.

But do not print or copy the receiving array, DMA can normally receive data, why?

Regards,

Li 3