/*==================================================================================================
*   Project              : RTD AUTOSAR 4.7 
*   Platform             : CORTEXM
*   Peripheral           : SIUL2
*   Dependencies         : none
*
*   Autosar Version      : 4.7.0
*   Autosar Revision     : ASR_REL_4_7_REV_0000
*   Autosar Conf.Variant :
*   SW Version           : 4.0.0
*   Build Version        : S32K3_S32M27x_AUTOSAR_R21-11_RTD_4_0_0_D2311_ASR_REL_4_7_REV_0000_20231128
*
*   Copyright 2020 - 2023 NXP
*
*   NXP Confidential. This software is owned or controlled by NXP and may only be
*   used strictly in accordance with the applicable license terms. By expressly
*   accepting such terms or by downloading, installing, activating and/or otherwise
*   using the software, you are agreeing that you have read, and that you agree to
*   comply with and are bound by, such license terms. If you do not agree to be
*   bound by the applicable license terms, then you may not retain, install,
*   activate or otherwise use the software.
==================================================================================================*/

#ifndef SIUL2_PORT_IP_CFG_H
#define SIUL2_PORT_IP_CFG_H

/**
*   @file      Siul2_Port_Ip_Cfg.h
*
*   @addtogroup Port_CFG
*   @{
*/

#ifdef __cplusplus
extern "C"{
#endif


/*==================================================================================================
                                         INCLUDE FILES
 1) system and project includes
 2) needed interfaces from external units
 3) internal and external interfaces from this unit
==================================================================================================*/
#include "S32K312_SIUL2.h"
#include "Siul2_Port_Ip_Types.h"

/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define SIUL2_PORT_IP_VENDOR_ID_CFG_H                       43
#define SIUL2_PORT_IP_AR_RELEASE_MAJOR_VERSION_CFG_H        4
#define SIUL2_PORT_IP_AR_RELEASE_MINOR_VERSION_CFG_H        7
#define SIUL2_PORT_IP_AR_RELEASE_REVISION_VERSION_CFG_H     0
#define SIUL2_PORT_IP_SW_MAJOR_VERSION_CFG_H                4
#define SIUL2_PORT_IP_SW_MINOR_VERSION_CFG_H                0
#define SIUL2_PORT_IP_SW_PATCH_VERSION_CFG_H                0

/*==================================================================================================
*                                     FILE VERSION CHECKS
==================================================================================================*/
/* Check if the files Siul2_Port_Ip_Cfg.h and Siul2_Port_Ip_Types.h are of the same version */
#if (SIUL2_PORT_IP_VENDOR_ID_CFG_H != SIUL2_PORT_IP_TYPES_VENDOR_ID_H)
    #error "Siul2_Port_Ip_Cfg.h and Siul2_Port_Ip_Types.h have different vendor ids"
#endif
/* Check if Siul2_Port_Ip_Cfg.h and Siul2_Port_Ip_Types.h are of the same Autosar version */
#if ((SIUL2_PORT_IP_AR_RELEASE_MAJOR_VERSION_CFG_H    != SIUL2_PORT_IP_TYPES_AR_RELEASE_MAJOR_VERSION_H) || \
     (SIUL2_PORT_IP_AR_RELEASE_MINOR_VERSION_CFG_H    != SIUL2_PORT_IP_TYPES_AR_RELEASE_MINOR_VERSION_H) || \
     (SIUL2_PORT_IP_AR_RELEASE_REVISION_VERSION_CFG_H != SIUL2_PORT_IP_TYPES_AR_RELEASE_REVISION_VERSION_H) \
    )
    #error "AutoSar Version Numbers of Siul2_Port_Ip_Cfg.h and Siul2_Port_Ip_Types.h are different"
#endif
/* Check if Siul2_Port_Ip_Cfg.h and Siul2_Port_Ip_Types.h are of the same Software version */
#if ((SIUL2_PORT_IP_SW_MAJOR_VERSION_CFG_H != SIUL2_PORT_IP_TYPES_SW_MAJOR_VERSION_H) || \
     (SIUL2_PORT_IP_SW_MINOR_VERSION_CFG_H != SIUL2_PORT_IP_TYPES_SW_MINOR_VERSION_H) || \
     (SIUL2_PORT_IP_SW_PATCH_VERSION_CFG_H != SIUL2_PORT_IP_TYPES_SW_PATCH_VERSION_H)    \
    )
    #error "Software Version Numbers of Siul2_Port_Ip_Cfg.h and Siul2_Port_Ip_Types.h are different"
#endif
/*==================================================================================================
                                           CONSTANTS
==================================================================================================*/

/*==================================================================================================
                                      DEFINES AND MACROS
==================================================================================================*/
#define SIUL2_MSCR_SSS_MASK                      (0xFU)
#define SIUL2_MSCR_SSS_SHIFT                     (0U)
#define SIUL2_MSCR_SSS_WIDTH                     (4U)
#define SIUL2_MSCR_SSS(x)                        (((uint32)(((uint32)(x)) << SIUL2_MSCR_SSS_SHIFT)) & SIUL2_MSCR_SSS_MASK)

#define SIUL2_MSCR_SRE_MASK                      (0x4000U)
#define SIUL2_MSCR_SRE_SHIFT                     (14U)
#define SIUL2_MSCR_SRE_WIDTH                     (1U)
#define SIUL2_MSCR_SRE(x)                        (((uint32)(((uint32)(x)) << SIUL2_MSCR_SRE_SHIFT)) & SIUL2_MSCR_SRE_MASK)


/*! @brief Definitions for PortContainer_0_BOARD_InitPeripherals Functional Group */

/*! @brief User number of configured pins */
#define NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals 36

#define PORT_START_SEC_CONFIG_DATA_UNSPECIFIED
#include "Port_MemMap.h"

/*! @brief User configuration structure */
extern const Siul2_Port_Ip_PinSettingsConfig g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals[NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals];

#define PORT_STOP_SEC_CONFIG_DATA_UNSPECIFIED
#include "Port_MemMap.h"

/*! @brief Defines for user pin and port configurations */
#define MCU_EC_SPI2_CS_PIN      9u
#define MCU_EC_SPI2_CS_PORT     PTB_H_HALF
#define MCU_EC_SPI2_Clk_PIN     13u
#define MCU_EC_SPI2_Clk_PORT    PTB_H_HALF
#define MCU_EC_SPI2_Sin_PIN     12u
#define MCU_EC_SPI2_Sin_PORT    PTB_H_HALF
#define MCU_EC_SPI2_Sout_PIN    11u
#define MCU_EC_SPI2_Sout_PORT   PTB_H_HALF
#define GPIO_2_PIN              2u
#define GPIO_2_PORT             PTA_L_HALF
#define GPIO_3_PIN              3u
#define GPIO_3_PORT             PTA_L_HALF
#define ADC0_P2_PIN             8u
#define ADC0_P2_PORT            PTA_L_HALF
#define ADC0_P7_PIN             9u
#define ADC0_P7_PORT            PTA_L_HALF
#define ADC1_P1_PIN             13u
#define ADC1_P1_PORT            PTA_L_HALF
#define ADC1_P7_PIN             15u
#define ADC1_P7_PORT            PTA_L_HALF
#define ADC0_P1_PIN             0u
#define ADC0_P1_PORT            PTD_L_HALF
#define ADC1_P3_PIN             1u
#define ADC1_P3_PORT            PTE_L_HALF
#define ADC1_P5_PIN             2u
#define ADC1_P5_PORT            PTE_L_HALF
#define ADC0_P5_PIN             10u
#define ADC0_P5_PORT            PTE_L_HALF
#define ADC0_P6_PIN             11u
#define ADC0_P6_PORT            PTE_L_HALF
#define ADC0_P4_PIN             0u
#define ADC0_P4_PORT            PTE_H_HALF
#define eMIOS_0_CH0_X_PIN       12u
#define eMIOS_0_CH0_X_PORT      PTB_L_HALF
#define eMIOS_0_CH1_X_PIN       13u
#define eMIOS_0_CH1_X_PORT      PTB_L_HALF
#define eMIOS_0_CH2_G_PIN       14u
#define eMIOS_0_CH2_G_PORT      PTB_L_HALF
#define eMIOS_0_CH3_G_PIN       15u
#define eMIOS_0_CH3_G_PORT      PTB_L_HALF
#define eMIOS_1_CH17_Y_PIN      4u
#define eMIOS_1_CH17_Y_PORT     PTD_H_HALF
#define eMIOS_1_CH18_Y_PIN      5u
#define eMIOS_1_CH18_Y_PORT     PTD_H_HALF
#define eMIOS_1_CH19_Y_PIN      6u
#define eMIOS_1_CH19_Y_PORT     PTD_H_HALF
#define eMIOS_1_CH20_Y_PIN      7u
#define eMIOS_1_CH20_Y_PORT     PTD_H_HALF
#define eMIOS_1_CH21_Y_PIN      8u
#define eMIOS_1_CH21_Y_PORT     PTD_H_HALF
#define eMIOS_1_CH23_X_PIN      10u
#define eMIOS_1_CH23_X_PORT     PTD_H_HALF
#define PTD17_LPUART_2_RX_PIN   1u
#define PTD17_LPUART_2_RX_PORT  PTD_H_HALF
#define PTE12_LPUART_2_TX_PIN   12u
#define PTE12_LPUART_2_TX_PORT  PTE_L_HALF

/*==================================================================================================
                                           ENUMS
==================================================================================================*/

/*==================================================================================================
                               STRUCTURES AND OTHER TYPEDEFS
==================================================================================================*/

/*==================================================================================================
                               GLOBAL VARIABLE DECLARATIONS
==================================================================================================*/

/*==================================================================================================
                               FUNCTION PROTOTYPES
==================================================================================================*/

#ifdef __cplusplus
}
#endif

#endif /* SIUL2_PORT_IP_CFG_H */

