Hi HXP,
S32K312 POR_WDG is what, how to use.
Hi @li3,
The Power-on Reset Watchdog is a module for added monitoring to the chip. If the chip is stuck in reset or standby for a determined time, the watchdog generates a power-on reset to recover it.
You can refer to the RTD example by importing it from S32DS:
Each 1 second, the SWT timeout expired and the SWT interrupt will reset the counter by writing the service sequence.
Best regards,
Julián
Hi NXP,
What is the Reset monitoring control register?
Is it to monitor whether Reset can succeed?
Best regards,
Li 3.
Hi NXP,
Please help me answer the following three questions.
1.I can't find the control register for reset monitor. I don't know how to turn on or off the reset monitoring function of POR_WDG. Please tell me the location of the register.
2. How does the reset monitoring function detect that the system is stuck in the reset sequence? Does it detect registers that have not been successfully reset?
3.The reset monitoring function indicates that after POR_WDG times out, the system deadlock position can be captured in DCM's DCMROPPn register. Can these states only let us know the system deadlock position after POR_WDG times out? Or is it the state of DCM's DCMROPPn register that determines the POR_WDG timeout?
Best regards,
Li 3.
Hi @li3,
1. Please refer to the DCF clients file attached to the reference manual.
2. The Watchdog timer has a configurable threshold, if the chip does not exit the reset sequence within this time, the POR_WDG initiates a power-on-reset. You can monitor the WDG status from the DCMROPPn register.
3. This register only captures the status of the functional reset sequence process when POR_WDG overflows.
Since the POR_WDG is part of the DCF client safety function, you can also look into the Safety Manual for S32K3 in "Secure Files" from the S32K3 Auto General-Purpose MCUs, documentation.
Best regards,
Julián
