S32K144W GPIO port output abnormal delay/unevenness

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S32K144W GPIO port output abnormal delay/unevenness

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607 次查看
Caihong_Liu
Contributor I

Hello,

We wish to use S32K144W to collect some ADC data and send then to a 8 bit flash chip. Currently we have a S32K14WEVB-Q064 evaluation board and the Port D 0-7 were chosen to output the 8-bit data. During the experiments I found that the GPIO D.2 and D.3 have a very high delay (almost 17us), which limites the data rate. I tried to write to the PTD->PDOR register and using DMA to move data to that register. Both methods all showed that problem.

The following pictures show the waveform from oscilloscope. The D.2 and D.3 acts incorrectly at high data rate. At low data rate it shows a ~5us delay at rising edge and ~17us delay at falling edge. All other GPIOs act normally. Is there any solution to this?highdelay1.pnghighdelay3.png

Thank you,

Caihong

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597 次查看
Senlent
NXP TechSupport
NXP TechSupport

Hi@Caihong_Liu

   Maybe you can consider the impact on the hardware. The hardware connection of PTD2&PTD3 is different from other ports.

Senlent_2-1659320190313.png

Senlent_1-1659320091442.png

I suggest you replace other ports and test again, or remove the two resistors R659 and R660 and test again

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586 次查看
Caihong_Liu
Contributor I

Hi Senlent,

I removed the two resistors and the problem is solved. Can't believe the buttons caused so high parasitic capacitance. Thank you!

 

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598 次查看
Senlent
NXP TechSupport
NXP TechSupport

Hi@Caihong_Liu

   Maybe you can consider the impact on the hardware. The hardware connection of PTD2&PTD3 is different from other ports.

Senlent_2-1659320190313.png

Senlent_1-1659320091442.png

I suggest you replace other ports and test again, or remove the two resistors R659 and R660 and test again

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