S32K144 LPUART WITH FIFO

[raviranjankumar]

Hi,

      I am working on S32K144 board. I want to use UART in full duplex mode. So I implemented FIFO but while receiving RDRF is not getting set, this is new for me so I have some query about FIFO in UART.

I followed these steps :

/* Get fifo size */
u8_lFIFOSize = (p_stgUartRegsAccess[en_lUartCh]->FIFO & UART_FIFO_RXFIFOSIZE_MSK);

if (0 != u8_lFIFOSize)
{
        /* Buffer size is 2 ^ (TXFIFOSIZE + 1) */
        u8_lFIFOSize = (1 << (u8_lFIFOSize + 1));

        /* Set FIFO watermark to FIFO_SIZE / 2 */
        p_stgUartRegsAccess[en_lUartCh]->WATER |= ((u8_lFIFOSize >> 1) << UART_FIFO_RXWATER_OFFSET);

        /* Enable Uart TX, RX FIFO */
        p_stgUartRegsAccess[en_lUartCh]->FIFO |= (1 << UART_FIFO_RXFE_OFFSET);

        /* Enable interrupt for Rx FIFO overflow and Rx FIFO underflow */
        p_stgUartRegsAccess[en_lUartCh]->FIFO |= (1 << UART_FIFO_RXUFE_OFFSET);
        //p_stgUartRegsAccess[en_lUartCh]->FIFO |= (1 << UART_FIFO_TXOFE_OFFSET);

        /* Clear FIFO overflow and underflow flags */
        p_stgUartRegsAccess[en_lUartCh]->FIFO |= (1 << UART_FIFO_RXUF_OFFSET);
        p_stgUartRegsAccess[en_lUartCh]->FIFO |= (1 << UART_FIFO_TXOF_OFFSET);

        /* Flush RX FIFO */
        p_stgUartRegsAccess[en_lUartCh]->FIFO |= (1 << UART_FIFO_RXFLUSH_OFFSET);

        /* Clear underflow flag */
        p_stgUartRegsAccess[en_lUartCh]->FIFO |= (1 << UART_FIFO_RXUF_OFFSET);

}

1. FIFO size is fixed 4-word. So how TX WATER and RXWATER will affect the transfer?

2. How to find that how many times I should read DATA register?

3. While Initializing UART,  RXUF flag is set. I am unable to clear by writing 1. So after enabling RXUFE every time I am getting Rx interrupt but RDRF flag is 0 only. 

4. Should I Enable Receive Ideal empty?

Please give me a clear procedure to make it work with FIFO. Example codes are also without FIFO so if any sample code for this will be better.

Please help.

Thanks and Regards,

Ravi Ranjan Kumar.

[danielmartynek]

Hi,
Unfortunately, we don’t have any UART example with FIFO.
RXWATER specifies when RDRF bit gets set. When the number of datawords in the RX FIFO is greater than RXWATER, RDRF is set.
For proper operation, the value in RXWATER must be set to be less than the receive FIFO size as indicated by FIFO[RXFIFOSIZE].
You can read the data register until RXEMPT in FIFO register is set (RX FIFO is empty) or read RXCOUNT in WATER register to get the number of datawards in the FIFO.
The RXUF flag is set when the data register is read while the FIFO is empty.

Please note that the debugger reads the data register as well if you have the register view open and this sets the flag.

Regards,
Daniel

[raviranjankumar]

Hi Daniel,

         Thanks for your valuable Information.

Regards,

Ravi Ranjan