S32K142 ECC Clarifications

[iniya]

Hi,

I am using S32K142. Activated the ECC using ERM registers as below,

---------------------------------------- code snippet start-------------------------------------------------

// IRQ48-LPIT0 ch0: clr any pending IRQ
S32_NVIC->ICPR[ERM_single_fault_IRQn/32] = (uint32_t)(1) << (ERM_single_fault_IRQn % 32);
// IRQ48-LPIT0 ch0: enable IRQ
NVIC_EnableIRQ(ERM_single_fault_IRQn);
// IRQ48-LPIT0 ch0: priority 11 of 0-15
NVIC_SetPriority(ERM_single_fault_IRQn, 0x09);

// IRQ48-LPIT0 ch0: clr any pending IRQ//
S32_NVIC->ICPR[ERM_double_fault_IRQn/32] = (uint32_t)(1) << (ERM_double_fault_IRQn % 32);
// IRQ48-LPIT0 ch0: enable IRQ
NVIC_EnableIRQ(ERM_double_fault_IRQn);
// IRQ48-LPIT0 ch0: priority 11 of 0-15
NVIC_SetPriority(ERM_double_fault_IRQn, 0x09);

// SRAM ECC Activation
ERM->CR0 = (ERM_CR0_ENCIE0_MASK |
ERM_CR0_ENCIE1_MASK |
ERM_CR0_ESCIE0_MASK |
ERM_CR0_ESCIE1_MASK);

---------------------------------------- code snippet end-------------------------------------------------

ECC single and double bit error is tested with EIM, Interrupts are getting registered.

Now, below are my doubts,

In Reference Manual, it is mentioned, that

"If an uninitialized memory address is read, it is likely the read will result in a multiple-bit ECC error and an errored transaction on the AHB."

Question 1: SRAM is uninitialised and now, i read the entire SRAM after ECC Initialisation. Neither single nor multi bit ECC error occurs. Is it acceptable? since the datasheet specifies otherwise.

In summary, even without RAM initialisation, i dont see any ECC error. Is it correct or Did i miss any other hardware register configuration?

Question 2: S32K142 supports SRAM_L(0x1FFFC000 - 0x1FFFFFFF) and SRAM_U(0x20000000 - 0x20002FFF). Data access from memory 0x20003000 - 0x20003FFF results in single or multi bit ECC error. Why is this happening? Honestly, what is this area? is it undefined/reserved? Is the reported behaviour expected?

Kindly support at the earliest.

[davidtosenovjan]

1) ECC is being initialized by start-up code by writing of any value. It is enough to completely define ECC code for data unit. If this is omitted, you should see invalid values (you can see characters like "XX" or "??") in a debugger.

2) In this case you are out of range, you are reading "reserved" address space. An access to reserved area may exhibit in multiple ways. In general we could say an access to reserved area may lead in unpredictable results and it is use out of specification. Mostly probably you will see bus error.

[iniya]

Hello @davidtosenovjan , Thank you for the reply

Answer 2 is fine.

Answer 1:

1. Do you mean that any single write to particular SRAM location (say 0x1FFFC000) will initialize the ECC code for every 32bit data field in the entire SRAM memory (0x1FFFC000 to 0x20002FFF), thereby giving correct ECC code, when any location in SRAM is read?

2. According to Data Sheet, 7 bit ECC code is generated for every 32 bit data field.

Example, 1KB memory has 32*32bit data field, thereby 32*7 = 224 bits of ECC code is available. 

Is the above understanding correct?

[davidtosenovjan]

1) I mean it is needed to write all 32-data fields in the loop to have SRAM properly initialized.

2) Yes, it is correct calculation (for 1Kbit memory). Just noting ECC field is hidden memory for user perspective. It does not affect addressing anyhow.

[iniya]

@danielmartynek , @lukaszadrapa @petervlna ,

Hello All,

Can you please support in this topic ?