S32K116_EVB Clock output

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S32K116_EVB Clock output

1,214件の閲覧回数
kwakd_y
Contributor III
I want to use clock out with S32K116_EVB.
I seted it as follows, but it does not work.
Please respond what is the problem.
void CLKOUT_init(void)
{
 PCC->PCCn[PCC_PORTB_INDEX ] |=PCC_PCCn_CGC_MASK;  /* Enable clock for PORTB */
 PTB->PDDR |= (1<<5);        /* Data Direction= output (default) */ 
 PORTB->PCR[5] |= PORT_PCR_MUX(5);             /* Port B5: MUX = CLKOUT */

SIM->CHIPCTL |= SIM_CHIPCTL_CLKOUTSEL(8);
SIM->CHIPCTL |= SIM_CHIPCTL_CLKOUTDIV(0); //Output clock divide by 1
SIM->CHIPCTL |= SIM_CHIPCTL_CLKOUTEN(1); //Enable CLKOUT
}
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1,057件の閲覧回数
dianabatrlova
NXP TechSupport
NXP TechSupport

Hello,

The "SIM->CHIPCTL |= SIM_CHIPCTL_CLKOUTSEL(8); " means that you have chosen the SPLLDIV2_CLK option as CLKOUT.

However, the Phase-locked loop (PLL) is not available for the S32K11x product series.

I would like to point you to the Reference Manual rev 9. section "27.2 High level clocking diagram" note number 3.

"3. For S32K11x, inputs and muxes connected to PCC are Reserved. Also, SPLLDIVx_CLK are Reserved as indicated in RED"

Best Regards,

Diana

1,057件の閲覧回数
MarvinLiu
Contributor II

Thanks for your suggestion!

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