S32K ADC，What is Source impedance(Rs) when fadck=40MHz

[Muskz]

About S32K ADC,Frome datasheet for S32K devices, ,we know Source impedance(Rs)  max is 5K,conditions is fadck < 4MHz.

Can I understand it this way? If I use an adc clock that is less than 4M, the maximum allowable Rs for external circuits is 5k.
If I use an adc clock of 40M, what should be the Rs? Why is it not stated in the manual, should it be larger or smaller than 5k?

I have read the manual AN12217, S32K1xx ADC guidelines, spec and configuration, but I haven't found any useful answers. Perhaps my level is not high enough

Thank you.

[Muskz]

Thank you very much for the information you provided. I will read the relevant documents.

[Robin_Shen · Accepted solution]

Hi Muskz,

Sorry. DataSheet does not give the source impedance (Rs) at fadck=40MHz.

Please read the AN4373 Cookbook for SAR ADC Measurements mentioned in AN12217. I think it should be smaller than 5k.

Best Regards,
Robin
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