Not Able to Generate required frequency of PWM

[PratikY]

Hello,

I am using the S32K344EVB-Q257 board. In which I am using emios 1 for PWM output generation. My Core frequency is 160 Mhz. I am able to divide the clock up to 16, but if I divide it to more than 17, the PWM output frequency is not generating as expected. As per TRM, I should be able to divide frequency up to 254(using Prescaler), but in firmware, I am able to divide it with only 16(InternalPs, InternalPsAlternate ). 

To calculate generated PWM frequency I am using the below calculation

EMIO_CLOCK

OneTick = 1/EMIO_CLOCK

up_time = oneTick*upcount
down_time = oneTick*downcount

oneCycle = uptime+downtime

pwm_freq = 1/oneCycle

My actual goal is to generate a PWM of 45 Hz, for that, I have to set Prescaler to 54(for 160 Mhz sys clock) if I set Prescaler(InternalPs, InternalPsAlternate )  to 54 i.e. EMIOS freq = 2.96MHz, but I am getting 348.7 Hz PWM signals instead of 45 Hz.

My PWM configuration is as follows.

const Emios_Pwm_Ip_ChannelConfigType Emios_Pwm_Ip_BOARD_InitPeripherals_I1_Ch22 =
{
/* .ChannelId */ 22U,
/* .Mode */ EMIOS_PWM_IP_MODE_OPWFMB_FLAG,
/* .Timebase */ EMIOS_PWM_IP_BUS_INTERNAL,
/* .DebugMode */ (boolean)FALSE,
/* .OutputDisableSource */ EMIOS_PWM_IP_OUTPUT_DISABLE_NONE,
/* .InternalPs */ 53,
/* .InternalPsAlternate */ 53,
/* .InternalPsSrc */ EMIOS_PWM_IP_PS_SRC_PRESCALED_CLOCK,
/* .OutputPolarity */ EMIOS_PWM_IP_ACTIVE_HIGH,
/* .IrqMode */ EMIOS_PWM_IP_NOTIFICATION_DISABLED,
/* .UserCallback */ {
/* .CbFunction */ NULL_PTR,
/* .CbParameter */ NULL_PTR
},
/* .PeriodCount */ 32768U,
/* .DutyCycle */ 16384U,
/* .PhaseShift */ 0U,
/* .DeadTime */ 0U,
/* .TriggerPosition */ 0U
};

Is there anything I have missed misconfigured or misunderstood? Let me know if anyone needs more information.

Can anyone help me with it?

[PetrS]

Hi,

there is also global prescaler within eMIOS module, which you need to use to lower freq on which eMIOS channel counter is clocked.
As you mentioned, eMIOS module is clocked from CORE_CLK (up to 160Mhz). eMIOS divides this clock by the global prescaler (MCR[GPRE] + 1) and routes the resulting prescaled clock output to the channel internal prescaler (Cn[UCPRE] + 1). Thus channel internal counter counts (CORE_CLK/global prescaler/internal prescaler) clock. Channel offers also extended prescaler, which you have used.

So configure global prescaler too in eMIOS_Mcl_Ip component and initialize Emios_Mcl driver using Emios_Mcl_Ip_Init function.

BR, Petr

[PratikY]

Thank you so much @PetrS for quick response.

I am able to generate the required frequency by changing the global Prescaler as suggested by @PetrS.