I would like an interrupt to be generated at the end of conversion of the ADC but I am only able to see these interrupts being serviced on core0 on my s32k322.
I have set the Target core for the ADC instance I am working with to core 1 (unchecked M7_0 and checked M7_1) in the Config Tool. If I enable core0 as target for these interrupts, the interrupts get triggered as expected, calling the ISR.
Is there any additional setting/mode required to allow servicing of ISRs on the cores other than core0? I am also unable to see the configuration being written to the IRSPRC registers as they all show up as "- not read -" as shown in the attached screenshot.
