FTFC Program Once command

[enricoantonioli]

I'm using the S32K144 evaulation board and I don't understand the usage of the FTFC "Program Once Command".

Someone has some idea of what should be programmed in the Program Once Field of 64 bytes of the program flash 0 IFR memory with the command Once?

The reference manual doesn't describe the meaning of the content of the 64 bytes of the Program Once Field of the Program IFR 0.

After reading the contents of the 64 bytes with the Read Once command, how can I interpret their contents?

Thanks in advance.

E.

[zky]

Hi,Mr Enrico

   Would you pls do me some favor about " program section command".

   I do not know how to write my date to FlexRam.

Thanks.

[enricoantonioli]

Hi,

unfortunately I do not think I understood your question well.
The following is an example of how I implemented the "Program Section" command:

/* ========================================================================== */
/*                                                                            */
/* Execute the PGMSEC FTFC command                                            */
/* Programs the data found in the section program buffer to previously erased */
/* locations in the flash memory (Address must be 128bit-aligned in PFlash    */
/* or 64-bit aligned in DFlash)                                               */
/*                                                                            */
/* retval  WAITING, SUCCESSFUL e FAILED                                       */
/*                                                                            */
/* ========================================================================== */
UINT8 ProgramSectionCommand(UINT32 address, UINT8 *buff, UINT16 size)
{
  register UINT8 res;
  UINT16 number;/* Number of double-phrases (128bit) for PFlash and phrases (64bit) for DFlash */
 
  if ((FTFC->FSTAT&FTFC_FSTAT_CCIF_MASK)==0)/* Waiting for previous command completed */
    return WAITING;

  if ((address>=PFLASH_START_ADDR)&&(address<=PFLASH_END_ADDR))
  {
    /* Check if destination address is aligned or not */
    if ((address&0x0000000F)!=0)/* Must be 128bit aligned */
      return FAILED;
    number = size/8;/* Number of double-phrases */
  }
  else if ((address>=DFLASH_START_ADDR)&&(address<=DFLASH_END_ADDR))
  {
    /* Check if destination address is aligned or not */
    if ((address&0x00000007)!=0)/* Must be 64bit aligned */
      return FAILED;
    number = size/4;/* Number of phrases */
    address |= (1<<23);/* bit 23 of the command address select between PFlash (0) and DFlash (1) */
  }
  else
  {
    return FAILED;
  }

  if (size>((FLEXRAM_END_ADDR-FLEXRAM_START_ADDR+1)/4))/* The maxsize of the section program buffer must be less than 1/4 FlexRAM size */
    return FAILED;

  /* Set FlexRAM function command to make the FlexRAM available As traditional RAM */
  do
  {
    res = SetFlexRamFunctionCommand(EEE_DISABLE, 0, NULL, NULL, NULL);/* Make FlexRAM available as RAM */
  }
  while (res==WAITING);
  if (res==SUCCESSFUL)
  {
    memcpy((void *)FLEXRAM_START_ADDR, buff, size);

    /* Clear old errors */
    FTFC->FSTAT = (FTFC_FSTAT_FPVIOL(1)|
                   FTFC_FSTAT_ACCERR(1)|
                   FTFC_FSTAT_RDCOLERR(1));

    /* Write FCCOB registers with the required command parameters */
    SET_FCCOB0(PGMSEC);
    SET_FCCOB1(GET_BIT_23_16(address));
    SET_FCCOB2(GET_BIT_15_08(address));
    SET_FCCOB3(GET_BIT_07_00(address));
    SET_FCCOB4(GET_BIT_15_08(number));
    SET_FCCOB5(GET_BIT_07_00(number));

    DISABLE_INTERRUPTS();
      FTFC->FSTAT = FTFC_FSTAT_CCIF(1); /* Clear the CCIF flag to launch the command */
      while((FTFC->FSTAT&FTFC_FSTAT_CCIF_MASK)==0); /* Waiting for command completed */
    ENABLE_INTERRUPTS();

    /* Check if an error is occurred */
    if ((FTFC->FSTAT&(FTFC_FSTAT_MGSTAT0_MASK|/* Run-time errors */
                      FTFC_FSTAT_FPVIOL_MASK| /* Protection error */
                      FTFC_FSTAT_ACCERR_MASK| /* Access error */
                      FTFC_FSTAT_RDCOLERR_MASK))!=0U)/* Read Collision Error */
      res = FAILED;
    else
      res = SUCCESSFUL;
  }

  if (emulatedEEpromEnabled==TRUE)
  {
    do
    {
      res = SetFlexRamFunctionCommand(EEE_ENABLE, 0, NULL, NULL, NULL);/* Make FlexRAM available for emulated EEPROM */
    }
    while (res==WAITING);
  }

  return res;
}

Hoping to help you,

Best regards

E.

[zky]

Hi

   Thanks for your help.

In your code,

would you please tell me some value of your macro define?

such as below.

"EEE_DISABLE" = 0xff ?

"FLEXRAM_START_ADDR" = 0x14000000?

and in fact i am using swd interface to program the flash, i can use 

"programme phrase command" to program the whole flash before,

and now i am trying to improve speed by using"Program Section command",

but i do not know why i can not write date to flex ram.

Thanks again.

[enricoantonioli]

Hi,

here the definitions that I use in my source code:

/* FlexRAM function control definitions */
#define EEE_ENABLE 0x00U /* Make FlexRAM available for emulated EEPROM */
#define EEE_QUICK_WRITE 0x55U /* Make FlexRAM available for EEPROM quick writes */
#define EEE_STATUS_QUERY 0x77U /* EEPROM quick write status query */
#define EEE_COMPLETE_INTERRUPT_QUICK_WRITE 0xAAU /* Complete interrupted EEPROM quick write process */
#define EEE_DISABLE 0xFFU /* Make FlexRAM available as RAM */

/* PFlash, DFlash and FlexRAM memory address definitions */
#define FLEXRAM_START_ADDR 0x14000000
#define FLEXRAM_END_ADDR 0x14000FFF

#define PFLASH_START_ADDR (UINT32)0x00000000
#define PFLASH_END_ADDR (UINT32)0x0007FFFF

#define DFLASH_START_ADDR (UINT32)0x10000000
#define DFLASH_END_ADDR (UINT32)0x1000FFFF

For use FTFC Program Section Command you must:

• set the FlexRAM Function Command with Function Control Code 0xFF (make FlexRam available as traditional RAM)
• copy the data that you want to program in the "section program buffer" (lower quarter of FlexRAM. For example in S32K144 with 4KB of FlexRAM the section program buffer address are: 0x14000000-0x140003FF)
• execute the FTFC Program Section command "PGMSEC"

I hope I have helped you

Best regards

E

[danielmartynek]

Hi,
There are 8 phrases that can be programmed only once.
So it can be used for a device ID or some calibration data that are unique for each device and do not change over the lifetime of the device.

Regards,
Daniel

[enricoantonioli]

Hi Daniel,

thank you very much.

I don't understand the meaning of "Margin" in the margin FTFC read-1s commands.

Can you help me?

Can you suggest me any source code examples or application notes that can be help me?

I'm developing a bootloader on the S32K144 microprocessor.

I understand that if I use the Erase Flash Block command using a PFlash address (for example 0x8000) I erase all 512KBytes of the entire program flash?

Regards,

E.

[danielmartynek]

Hi Enrico,

Erased Flash cells are read as “1” and programmed as “0” and the Margin level is basically the threshold of the reading.
Some of the cells might be weakly programmed or erased. To check that the Flash has been erased or programmed properly, the Margin level can be adjusted.
So, a read with 1s Margin will be more sensitive to weakly erased cells and 0s Margin to weakly programmed cells.
You can refer, for instance, to AN3419 System Integrity Techniques for the S12XE, Chapter 3.

S32K has a few Flash commands that take a margin level parameter, please see Section 35.5.10 in the RM.

Yes, the Erase Flash Block command will erase the whole PFlash block.
See AN12130, Production Flash Programming Best Practices for S32K1xx MCUs, Section 3.2.3.

Regards,
Daniel

[enricoantonioli]

Hi Daniel,

thank you very much for your clear explanation.

I have only a last question: can you suggest me to disable cache during reprogramming procedure or not?

Can you explain me some C source code for that I can use to disable/enable the chace?

There is specific register for disable DFlash cache and Pflash cache ?

Thank you in advance

Best regards

E

[enricoantonioli]

Hi Daniel,

is it necessary to disable the program flash cache during reprogramming?

Can I use this source code?

MSCM->OCMDR[0] |= MSCM_OCMDR_OCM1(0b11); /* OCMDR1 */
MSCM->OCMDR[1] |= MSCM_OCMDR_OCM1(0b11); /* OCMDR2 */

Have you any suggestion?

Best regards,

E.

[danielmartynek]

Hi Enrico,
Sorry for the delay.
Yes, it is necessary and you can use this code.

The flash controller needs to be idle when writing to an OCMDRn register associated with Flash memory.
This means no read/erase/execute/etc operations from the Flash memory should be made while writing to the OCMDRn register associated with that memory. So do not execute the code from PFlash memory when you are disabling the PFlash buffer. 

Regards,
Daniel

[enricoantonioli]

Hi Daniel,

thank you very much.

I was left with a doubt:

if I understand the reference manual at pag. 695 it reports that if the PCCCR[ENCACHE] bit register is clear mean "Cache Disabled". At this point what does it means write the OCM1 bits in the OCMDR0 and OCMDR1 registers?

A stupid question: if the PCCCR[ENCACHE] bit is 0 implies that the cache is disabled or no?

The values of the OCM1 field in the OCMDRO and OCDMR1 registers is of two or four bits size?

Regards,

E.

[danielmartynek]

Hi Enrico,
These are two different things. There is LMEM Cache and FMC prefetch buffer.
Please read AN4745 Optimizing Performance on Kinetis K-series MCUs
http://cache.freescale.com/files/microcontrollers/doc/app_note/AN4745.pdf

OCM1 is a 2-bit field.

Regards,
Daniel