External clock signal levels

[JensFleischhacker]

I'm confused about the S32K1 datasheet and the 2 statements about the external clock

For low detection you need to be below 1.15V, for high above 0.7*VDD but on the other hand a Vexp_pp value of more than 0.8V is sufficient.

What kind of external clock signal levels are supported ? I have a 1.25V square wave signal is that suffiecent or do I need a VDD related signal ?

For S32K3 there are no levels define in the datasheet. Is that possible at all and if yes how should the signal look like. Same as for S32K1 ?

[davidtosenovjan]

Certainly it is expected square wave of level VDD for high and VSS for low. Do not compare it with internal oscillator, it is different mode.

Grey zone between VILmax and VIHmin is just transitory area (with included hysteresis).

In S32K3, requirements are the same that the digital/logic levels (VIL/VIH), it is just not specified separately.