Anybody knows how S32K322 run as single core0, but take use of the disabled core1's dtcm1?

Jennie_Jing · ‎07-27-2023

Hi, dear NXP supporters:

I'm working on a project based on S32K322, which is used S32K342 before. Nothing changed except the MCU, because the supply...

I still want to run single core0, Then I met a problem about memory lack( 322 is half of 342).

The good news is I can take use of the tcm of the disabled core1.

According to S32K3xx RM, in Charpter 3.4:

I have written all the related bits to 1.when mcu power up, and use the backdoor address of dtcm1 to access dtcm1.

But S32K322 (64K dtcm0 +64 k dtcm1) behave does not like dtcm0 when I use S32K342 (128Kb dtcm).

What is the sequence of this function? What did I miss?

IF someone has ever done this,please reply.

dmitry_buchynski · ‎07-28-2023

Hello @Jennie_Jing @danielmartynek
I'm dealing with the same problem but with k324 controller.
I have slightly modified Example-S32K314-DTCM1-Backdoor-RTD201-DS34-v2 and what I have found is that:
1) When CORE1 is enabled #define CM7_1_ENABLE 1 the memory seems to operate correctly, otherwise the memory content can be randomly changed to zero in random places.
2) When CORE1 is enabled the program executes only while debuging. After disconnecting the debugger and reseting the Uc the program seems to not run at all. I assume the debugger somehow halts CORE1. But when CORE1 is released it interfers with CORE0.
3) The lines from AN13388 under "Example 5. TCM Configured as System RAM" do not affect the behaviour. Tried to call them in "SetCore0Stack" in or in main, no effect. Maybe I don't understand their purpose correctly.
Debugged with Segger.
See the attached project s32k324.
@danielmartynek would appreciate any help and clarification on the behaviour.

Jennie_Jing · ‎08-01-2023

hi,@dmitry_buchynski Did you follow these steps in charpter 3.4 of RM?

I don't why I have not permission to upload images.

3.4
TCM as system memory
On multi–core device, all enabled core and non–core masters can use TCMs of the disabled core. In order to allow use of ITCM and DTCM of the disabled core as system memories the following steps must be executed by enabled core:
1.
Write 1 to MC_ME's PRTN2_COFB1_CLKEN[REQ62] field for Cortex-M7_0, PRTN2_COFB1_CLKEN[REQ63] field for Cortex-M7_1, PRTN2_COFB2_CLKEN[REQ64] field for Cortex-M7_2, and PRTN2_COFB2_CLKEN[REQ65] field for Cortex-M7_3. This enables the Cortex-M7 core's TCM
controller clock.
2.
. Write 1 to DCM_GPR's DCMRWF4[CM7_0_CPUWAIT] field for Cortex-M7_0, DCMRWF4[CM7_1_CPUWAIT] field for Cortex-M7_1, DCMRWF4[CM7_2_CPUWAIT] field for Cortex-M7_2, and DCMRWF4[CM7_3_CPUWAIT] field for Cortex-M7_3. This configures the core operation in Wait mode.
3.
Write 1 to MC_ME's PRTN0_CORE0_PCONF[CCE] field for Cortex-M7_0, PRTN0_CORE1_PCONF[CCE] field for Cortex-M7 _1, PRTN0_CORE4_PCONF[CCE] field for Cortex-M7_2, and PRTN0_CORE3_PCONF[CCE] field for Cortex-M7_3. This enables the Cortex-M7 core's clock.

And hi@danielmartynek . does these steps necessary? When?

when I debug with only core0 enabled, I can't see the register of core1, right?

for example, I cannot find the bit18 of DCMRWF4[CM7_3_CPUWAIT] at all.

dmitry_buchynski · ‎08-03-2023

Hello, @Jennie_Jing.
I have used the latest Example_S32K314_DTCM1_Backdoor_RTD201_DS34_v3 that @danielmartynek provided and it works.
The steps (at least some of them) mentioned in 3.4 of RM are executed in the startup_cm7.s file under the DTCM1_BD_Init section as I can see.

Jennie_Jing · ‎08-01-2023

sorry for mistake,

bit18 of DCMRWF4[CM7_3_CPUWAIT] ---should be-->bit18 of DCMRWF4[CM7_1_CPUWAIT]

the bits are set to 1 successfully, except this bit ( can't be found )

but still dtcm1 cannot work correctly. some regions are ???????, and cannot be clear to 0 entirely.

danielmartynek · ‎08-02-2023

Hi @Jennie_Jing,

Yes, this have to be enabled:

PRTN2_COFB1_CLKEN[REQ63]
DCMRWF4[CM7_1_CPUWAIT]
PRTN0_CORE1_PCONF[CCE]

I'm setting DCMRWF4[18]

#define DCM_GPR_DCMRWF4 0x402AC60C

/* CM7_1 Wait Mode */
LDR r1, =DCM_GPR_DCMRWF4
LDR r0, [r1]
LDR r2, =0x40000U
ORR r0, r2
STR r0, [r1]

And I see the bit set:

Although the register view in the debugger does not have the register.

Are you testing it on S32K324 (S32K314) or S32K322?

Which regions are ???????

Regards,

Daniel

Jennie_Jing · ‎08-07-2023

@danielmartynek hi,

I'm working on S32K322.

I can access itcm1 now, but dtcm1 still not work. Although I use the same way, tried both 64bits and 32bits write to init dtcm1.

we don't use the S32 Design Studio, we use our own way to compile and build, we don't have the startup_cm7.s file. So, I can't use your code directly, and I try to embed your assembly code into my C code in startup.c. but I'm not good at asm, I googled the method, and get some errors.

I want to ask if you kindly have the C code for DTCM1 init? Or the assembly code embedded in C code?

danielmartynek · ‎08-10-2023

Hi @Jennie_Jing,

I'm sorry for the delay, I was out of office for 2 days.

Do you mean such an inline asm code (GCC 10.2)?

uint32_t MCME_PRTN2_COFB1_CLKEN = 0x402DC534;
uint32_t DCM_GPR_DCMRWF4 = 0x402AC60C;
uint32_t MCME_PRTN0_CORE1_PCONF = 0x402DC160;
uint32_t MCME_PRTN0_CORE1_PUPD = 0x402DC164;
uint32_t MCME_CTL_KEY = 0x402DC000;
uint32_t MCME_PRTN1_PUPD = 0x402DC304;
uint32_t MCME_PRTN1_STAT = 0x402DC308;
uint32_t MCME_PRTN1_COFB0_CLKEN = 0x402DC330;
uint32_t MCME_PRTN1_COFB0_STAT = 0x402DC310;
uint32_t MCME_INV_KEY = 0xA50F;
uint32_t MCME_KEY = 0x5AF0;


__asm__(
/* Initialize DTCM1_BD ECC */
"ldr r0, =__DTCM1_BD_INIT \n\t"
"cmp r0, 0 \n\t"
/* Skip if __DTCM_INIT is not set */
"beq DTCM1_BD_LOOP_END \n\t"

/* Enable CM7_1 TCM */
"LDR r1, =MCME_PRTN2_COFB1_CLKEN \n\t"
"LDR r0, [r1] \n\t"
"LDR r2, =0x80000000U \n\t"
"ORR r0, r2 \n\t"
"STR r0, [r1] \n\t"

/* CM7_1 Wait Mode */
"LDR r1, =DCM_GPR_DCMRWF4 \n\t"
"LDR r0, [r1] \n\t"
"LDR r2, =0x40000U \n\t"
"ORR r0, r2 \n\t"
"STR r0, [r1] \n\t"

/* Enable CM7_1 clock */
"LDR r1, =MCME_PRTN0_CORE1_PCONF \n\t"
"LDR r0, [r1] \n\t"
"LDR r2, =0x1U \n\t"
"ORR r0, r2 \n\t"
"STR r0, [r1] \n\t"

/* Update register for CM7_1*/
"LDR r1, =MCME_PRTN0_CORE1_PUPD \n\t"
"LDR r0, [r1] \n\t"
"LDR r2, =0x1U \n\t"
"ORR r0, r2 \n\t"
"STR r0, [r1] \n\t"

/* Trigger update */
"ldr r0, =MCME_CTL_KEY \n\t"
"ldr r1, =MCME_KEY \n\t"
"str r1, [r0] \n\t"
"ldr r1, =MCME_INV_KEY \n\t"
"str r1, [r0] \n\t"
"ldr r1, =__INT_DTCM_1_BD_START \n\t"
"ldr r2, =__INT_DTCM_1_BD_END \n\t"

"subs r2, r1 \n\t"
"subs r2, #1 \n\t"
"ble DTCM1_BD_LOOP_END \n\t"

"movs r0, 0 \n\t"
"movs r3, 0 \n\t"
"DTCM1_BD_LOOP:"
" stm r1!, {r0,r3} \n\t"
" subs r2, #8 \n\t"
" bge DTCM1_BD_LOOP \n\t"
" nop \n\t"
"DTCM1_BD_LOOP_END: \n\t");

BR, Daniel