I want to verify that the following is true regarding IPU double buffer operations (my best interpretation of what the RM says):
When double buffering is used, EBA0 is the base address of buffer 0 and EBA1 is the base address of buffer 1. The addresses of these buffers are stored in the associated CPMEM mega-word (chans 23 and 27). The IPUx_CUR_BUF Register is a status register. It contains a 1-bit pointer to the current working buffer (EBA0 or EBA1) for each of the IPU DMA channels. The IPU automatically toggles the pointer at the end of a frame if the alternate buffer ready bit is set. If the alternate buffer is not ready, the toggle does not take place and the same buffer is used for the next frame.
If the ARM platform is writing into a double-buffered channel, it should check the status bit in IPUx_CUR_BUF in order to know which IPU buffer is currently being displayed. The ARM platform is only allowed to write into a buffer when a working DMA channel is not using it. After the ARM platform has finished drawing into a buffer, the corresponding bit in the IPUx_CH_BUF0_RDY or IPU_CH_BUF1_RDY Register should be set to show that the buffer is ready . The ARM platform can only set the bit (by writing a 1), but cannot clear it. When a bit in either IPUx_CH_BUF0_RDY or IPU_CH_BUF1_RDY is set, the bit for the alternate buffer is cleared.
Another question:
- What is the proper sequence to use in changing both the Ext Mem Buffer 0 and Buffer 1 addresses in CPMEM mega-word for channels 23 and 27 (when going to a complete different image ) – image is in a different set of foreground/background frame buffers. The RM in Table 37-15 states that these parameters cannot be changed if the corresponding channel is enabled.
