S32G399 CAN_PE_CLK config

[learnx]

hardware:s32g399ardb

sdk version: bp38

My question:
In uboot, use clk dump to query the llce_can_pe clock. The device tree of atf is configured with 40MHZ, which seems to be fine, but why is the value 0?

ATF dts config:

mc_cgm0: mc_cgm0@40030000 {

compatible = "nxp,s32cc-mc_cgm0";

reg = <0x0 0x40030000 0x0 0x3000>;

assigned-clocks =

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX0>,

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX1>,

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX2>,

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX3>,

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX4>,

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX5>,

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX7>,

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX8>,

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX9>,

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX10>,

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX12>,

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX14>,

<&plat_clks S32GEN1_CLK_MC_CGM0_MUX16>,

<&plat_clks S32GEN1_CLK_XBAR_2X>,

<&plat_clks S32GEN1_CLK_PER>,

<&plat_clks S32GEN1_CLK_FTM0_REF>,

<&plat_clks S32GEN1_CLK_FTM1_REF>,

<&plat_clks S32GEN1_CLK_CAN_PE>,

<&plat_clks S32GEN1_CLK_LIN_BAUD>,

<&plat_clks S32GEN1_CLK_GMAC0_TS>,

<&plat_clks S32GEN1_CLK_SPI>,

<&plat_clks S32GEN1_CLK_SDHC>,

<&plat_clks S32GEN1_CLK_QSPI_2X>;

assigned-clock-parents =

<&plat_clks S32GEN1_CLK_ARM_PLL_DFS1>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI0>,

<&plat_clks S32GEN1_CLK_FXOSC>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI1>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI1>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI1>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI2>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI3>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI4>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI5>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_DFS1>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_DFS3>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI7>;

assigned-clock-rates =

<0>,

<0>,

<0>,

<0>,

<0>,

<0>,

<0>,

<0>,

<0>,

<0>,

<0>,

<0>,

<0>,

<0>,

<80000000>,

<40000000>,

<40000000>,

<40000000>,

<125000000>,

<200000000>,

<100000000>,

<400000000>,

<S32GEN1_QSPI_2X_CLK_FREQ>;

};

periphpll: periphpll@4003c000 {

compatible = "nxp,s32cc-periphpll";

reg = <0x0 0x4003c000 0x0 0x3000>;

assigned-clocks =

<&plat_clks S32GEN1_CLK_PERIPH_PLL_MUX>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_VCO>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI0>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI1>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI2>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI3>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI4>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI5>,

<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI7>;

assigned-clock-parents =

<&plat_clks S32GEN1_CLK_FXOSC>;

assigned-clock-rates =

<0>,

<S32GEN1_PERIPH_PLL_VCO_FREQ>, <100000000>,

<80000000>, <40000000>,

<125000000>, <200000000>,

<125000000>, <100000000>;

};

accelpll: accelpll@40040000 {

compatible = "nxp,s32cc-accelpll";

reg = <0x0 0x40040000 0x0 0x3000>;

};

[Daniel-Aguirre]

Hi,

Have you enabled LLCE under your current build? Was it initialized under uboot?

Are you able to use LLCE when the log shows the 0 hz value?

We have used LLCE under BSP38.0 and have not seen problems with the communication.

Please, let us know.

[learnx]

Is it necessary to load the LLCE driver ko? I just want to initialize the LLCE clock

I use the prebuild image of s32g274ardb2 bsp33.0 and do not load the llce driver. I can see the configured values ​​in uboot.

[Daniel-Aguirre]

Hi,

Thanks for your feedback.

Since the BSP version is different, and we understand that there are several differences on regards of BSP33.0 and BSP38.0, the initialization of BSP38.0 might look into disabling (or not enabling) unused peripherals/clocks.

If you enable LLCE under BSP38.0, are you seeing any problems with it? Again, we understand that maybe under uboot LLCE clock may not be enabled, but under Linux itself LLCE should be working.

Please, let us know.