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- Re: S32G3 with DP83869 PFE PHY having bring up issues
S32G3 with DP83869 PFE PHY having bring up issues
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S32G3 with DP83869 PFE PHY having bring up issues
10-03-2024
11:10 AM
1,404 Views
minersrevolt
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We have a board that uses 3x TI DP83869 PHYs connected to the PFE interfaces using the 1.25 Gbps SGMII MAC. I am currently just trying to get PFE2 connected to SERDES0 XPCS0_1 running and I get a link up notification through ethtool and the partner PC I am communicating with also sees link up. However when the ethernet cable is unplugged the host PC recognizes the link goes down while the S32G does not, it remains active. Ethtool is also reporting that we are in MII mode when I expect it should be in MII-X mode; checking the TI datasheet and manually reading back MDIO registers I confirmed that it is enabled in SGMII mode.
When pinging between the S32G and the host machine neither partner is receiving packets according to ifconfig.
I'm concerned that perhaps the SERDES is not configured correctly to actually transfer packets between the S32G and the PHY. In U-Boot I get an error that XPCS0_1 and XPCS1_0 cannot both be SGMII but according to the reference manual it looks like that is a valid configuration, I'm not sure if that's related to what the current issue is but for now I overrode that error and returned a passing value on that check to keep U-Boot going.
Using the following NXP Automotive BSPs,
- Linux - bsp40.0-5.15.145-rt
- ATF - bsp40.0-2.5
- U-Boot - bsp40.0-2022.04
U-Boot has been modified to boot with the following hwconfig string,
CONFIG_S32CC_HWCONFIG="serdes0:mode=pcie&xpcs1,clock=int,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G,an=1;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=100;xpcs1_0:speed=1G,an=0;xpcs1_1:speed=1G,an=0"
When booting I see the following prints in U-Boot,
User OVERRIDE returning true: xpcs0_1 and xpcs 1_0 can't be both SGMII
s32cc_serdes_phy serdes@40480000: Using mode 2 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: INT Clock selected
s32cc_serdes_phy serdes@40480000: XPCS1 is in reset
s32cc_serdes_phy serdes@40480000: XPCS init failed
pci_s32cc pcie@40400000: Failed to get PHY 'serdes_lane0'
In: serial@401c8000
Out: serial@401c8000
Err: serial@401c8000
Board revision: RDB3
Net: No ethernet found.
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
15040520 bytes read in 629 ms (22.8 MiB/s)
Booting from mmc ...
44002 bytes read in 6 ms (7 MiB/s)
## Error: "fdt_fixups" not defined
## Flattened Device Tree blob at 83000000
Booting using the fdt blob at 0x83000000
Using Device Tree in place at 0000000083000000, end 000000008300dbe1
Disabling XPCS0_0
Failed to update XPCS1 for SerDes0
User OVERRIDE returning true: xpcs0_1 and xpcs 1_0 can't be both SGMII
Once Linux comes up I see the following with respect to the SERDES interface,
[ 3.209694] phy-s32cc-serdes 40480000.serdes: Using mode 2 for SerDes subsystem
[ 3.509824] phy-s32cc-serdes 40480000.serdes: XPCS1 is in reset
[ 3.509830] phy-s32cc-serdes 40480000.serdes: XPCS init failed
[ 3.510158] phy-s32cc-serdes 44180000.serdes: Using mode 3 for SerDes subsystem
[ 3.516233] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS1
[ 3.516252] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS0
[ 3.910364] s32cc-pcie 40400000.pcie: DBI R/W is not being enabled
[ 3.910949] s32cc-pcie 40400000.pcie: PCI Device and Vendor IDs could not be set
[ 4.305603] s32cc-pcie 40400000.pcie: DBI R/W is not being enabled
[ 4.517844] s32cc-pcie 40400000.pcie: Failed to stabilize PHY link
[ 4.517851] s32cc-pcie 40400000.pcie: Configuring as RootComplex
[ 4.517875] s32cc-pcie 40400000.pcie: host bridge /soc/pcie@40400000 ranges:
[ 4.517903] s32cc-pcie 40400000.pcie: IO 0x5ffffe0000..0x5ffffeffff -> 0x0000000000
[ 4.517919] s32cc-pcie 40400000.pcie: MEM 0x5800000000..0x5ffffdffff -> 0x0000000000
[ 4.517938] s32cc-pcie 40400000.pcie: Memory resource size exceeds max for 32 bits
[ 4.517967] s32cc-pcie 40400000.pcie: Resources exceed number of ATU entries (0)
[ 5.518109] s32cc-pcie 40400000.pcie: Phy link never came up
[ 5.518136] s32cc-pcie 40400000.pcie: iATU unroll: enabled
[ 5.518141] s32cc-pcie 40400000.pcie: Detected iATU regions: 6 outbound, 4 inbound
[ 6.516307] s32cc-pcie 40400000.pcie: Phy link never came up
[ 7.516421] s32cc-pcie 40400000.pcie: Phy link never came up
[ 7.516506] s32cc-pcie 40400000.pcie: PCI host bridge to bus 0000:00
[ 7.516513] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 7.516529] pci_bus 0000:00: root bus resource [mem 0x5800000000-0x5ffffdffff] (bus address [0x00000000-0x7fffdffff])
[ 7.516577] pci 0000:00:00.0: [16c3:4300] type 01 class 0x060400
[ 7.516600] pci 0000:00:00.0: reg 0x10: [mem 0x5800000000-0x58000fffff]
[ 7.516620] pci 0000:00:00.0: reg 0x38: [mem 0x5800000000-0x580000ffff pref]
[ 7.516722] pci 0000:00:00.0: supports D1
[ 7.516727] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
[ 7.520400] pci 0000:00:00.0: BAR 0: assigned [mem 0x5800000000-0x58000fffff]
[ 7.520411] pci 0000:00:00.0: BAR 6: assigned [mem 0x5800100000-0x580010ffff pref]
[ 7.520419] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[ 7.520723] pcieport 0000:00:00.0: PME: Signaling with IRQ 79
Then with respect to the PFEs,
[ 16.948142] pfeng: loading out-of-tree module taints kernel.
[ 16.955618] pfeng 46000000.pfe: PFEng ethernet driver loading ...
[ 16.955634] pfeng 46000000.pfe: Version: 1.3.0
[ 16.955639] pfeng 46000000.pfe: Driver commit hash: M4_DRIVER_COMMIT_HASH
[ 16.955643] pfeng 46000000.pfe: Multi instance support: disabled (standalone)
[ 16.955647] pfeng 46000000.pfe: Compiled by: 12.3.0
[ 16.955674] pfeng 46000000.pfe: Cbus addr 0x46000000 size 0x1000000
[ 16.955682] pfeng 46000000.pfe: nxp,fw-class-name: s32g_pfe_class.fw
[ 16.955688] pfeng 46000000.pfe: nxp,fw-util-name: s32g_pfe_util.fw
[ 16.955741] pfeng 46000000.pfe: netif name: pfe2
[ 16.955747] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:02
[ 16.955756] pfeng 46000000.pfe: netif(pfe2) linked phyif: 2
[ 16.955761] pfeng 46000000.pfe: netif(pfe2) mode: std
[ 16.955774] pfeng 46000000.pfe: netif(pfe2) HIFs: count 1 map 04
[ 16.955786] pfeng 46000000.pfe: EMAC2 interface mode: 4
[ 16.955928] pfeng 46000000.pfe: HIF channels mask: 0x0004
[[ 16.955962] pfeng 46000000.pfe: PFE port coherency enabled, mask 0x1e
16.956249] pfeng 46000000.pfe: Clocks: sys=300MHz pe=600MHz
[[ 16.956268] pfeng 46000000.pfe: Interface selected: EMAC0: 0xffffffff EMAC1: 0xffffffff EMAC2: 0x4
0[ 16.956966] pfeng 46000000.pfe: PFE controller reset done
;[ 16.957042] pfeng 46000000.pfe: TX clock on EMAC2 for interface sgmii installed
3[ 16.957076] pfeng 46000000.pfe: RX clock on EMAC2 for interface sgmii installed
2[ 16.957392] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34000000
m[ 16.957447] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34080000
[ 16.957507] pfeng 46000000.pfe: assigned reserved memory node pfebufs@83200000
[ 16.957535] pfeng 46000000.pfe: assigned reserved memory node pfebufs@835e0000
O[ 16.962902] pfeng 46000000.pfe: Firmware: CLASS s32g_pfe_class.fw [45040 bytes]
K[ 16.962911] pfeng 46000000.pfe: Firmware: UTIL s32g_pfe_util.fw [23252 bytes]
[ 16.962926] pfeng 46000000.pfe: PFE CBUS p0x46000000 mapped @ v0xffffffc00c000000 (0x1000000 bytes)
[ 16.962933] pfeng 46000000.pfe: HW version 0x101
16.962940] pfeng 46000000.pfe: Silicon S32G3
[[ 16.962947] pfeng 46000000.pfe: Fail-Stop mode disabled
0[ 16.965827] pfeng 46000000.pfe: PFE_ERRORS:Parity instance created
m[ 16.965838] pfeng 46000000.pfe: PFE_ERRORS:Watchdog instance created
][ 16.965844] pfeng 46000000.pfe: PFE_ERRORS:Bus Error instance created
[ 16.965849] pfeng 46000000.pfe: PFE_ERRORS:FW Fail Stop instance created
F[ 16.965854] pfeng 46000000.pfe: PFE_ERRORS:Host Fail Stop instance created
i[ 16.965859] pfeng 46000000.pfe: PFE_ERRORS:Fail Stop instance created
n[ 16.965866] pfeng 46000000.pfe: PFE_ERRORS:ECC Err instance created
i[ 16.965877] pfeng 46000000.pfe: BMU1 buffer base: p0xc0000000
s[ 16.965967] pfeng 46000000.pfe: BMU2 buffer base: p0x34000000 (0x80000 bytes)
h[ 16.967284] pfeng 46000000.pfe: register IRQ 75 by name 'PFE BMU IRQ'
e[ 16.967472] pfeng 46000000.pfe: Firmware .elf detected
d[ 16.967471] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x00000000f5cd3ead). Pool ready.
[ 16.967479] pfeng 46000000.pfe: Uploading CLASS firmware
16.967481] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x00000000d97e14d5). Pool ready.
[ 16.967486] pfeng 46000000.pfe: Selected FW loading OPs to load 8 PEs in parallel
0[ 16.987415] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8"
;[ 17.003088] pfeng 46000000.pfe: [FW VERSION] 1.8.0, Build: Nov 16 2023, 07:46:11 (nogitaaa), ID: 0x31454650
1[ 17.003377] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0
;[ 17.003419] pfeng 46000000.pfe: Uploading UTIL firmware
3[ 17.003423] pfeng 46000000.pfe: Selected FW loading OPs to load 1 PEs in parallel
9[ 17.005930] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8"
m[ 17.007013] pfeng 46000000.pfe: FW feature: drv_run_on_g3
V[ 17.007018] pfeng 46000000.pfe: FW feature: jumbo_frames
A[ 17.007024] pfeng 46000000.pfe: FW feature: software_vlan_table
S[ 17.007028] pfeng 46000000.pfe: FW feature: timestamping
T[ 17.007032] pfeng 46000000.pfe: FW feature: qos_mapping
[ 17.007037] pfeng 46000000.pfe: FW feature: core_functionality
:[ 17.007043] pfeng 46000000.pfe: FW feature: extended_features
[ 17.007047] pfeng 46000000.pfe: FW feature: flexible_router
I[ 17.007051] pfeng 46000000.pfe: FW feature: validate_hif_csum
n[ 17.007056] pfeng 46000000.pfe: FW feature: err051211_workaround
i[ 17.007061] pfeng 46000000.pfe: FW feature: IPsec
t[ 17.007067] pfeng 46000000.pfe: FW feature: l2_bridge_aging
i[ 17.007072] pfeng 46000000.pfe: FW feature: receive_malformed
a[ 17.007077] pfeng 46000000.pfe: FW feature: ptp_conf_check
l[ 17.007083] pfeng 46000000.pfe: FW feature: vlan_conf_check
i[ 17.007088] pfeng 46000000.pfe: FW feature: hash_load_spread
z[ 17.007093] pfeng 46000000.pfe: FW feature: ingress_vlan
e[ 17.007099] pfeng 46000000.pfe: FW feature: safety
[ 17.009543] pfeng 46000000.pfe: VLAN ID incorrect or not set. Using default VLAN ID = 0x01.
P[ 17.009548] pfeng 46000000.pfe: VLAN stats size incorrect or not set. Using default VLAN stats size = 20.
F[ 17.009629] pfeng 46000000.pfe: Software vlan hash table @ p0x20001278
E[ 17.009807] pfeng 46000000.pfe: Fall-back bridge domain @ 0x20000a80 (class)
s[ 17.009813] pfeng 46000000.pfe: Default bridge domain @ 0x20000a78 (class)
17.010812] pfeng 46000000.pfe: Routing table created, Hash Table @ p0xc00e0000, Pool @ p0xc00e8000 (65536 bytes)
[[ 17.010999] pfeng 46000000.pfe: Feature err051211_workaround: DISABLED
0[ 17.012501] pfeng 46000000.pfe: MDIO bus 0 disabled: Not found in DT
m[ 17.012508] pfeng 46000000.pfe: MDIO bus 1 disabled: Not found in DT
.[ 17.018954] pfeng 46000000.pfe: MDIO bus 2 enabled
[ 17.018964] pfeng 46000000.pfe: HIF0 not configured, skipped
[ 17.018969] pfeng 46000000.pfe: HIF1 not configured, skipped
[ 17.019232] pfeng 46000000.pfe: HIF2 enabled
[ 17.019237] pfeng 46000000.pfe: HIF3 not configured, skipped
[ 17.019331] pfeng 46000000.pfe pfe2 (uninitialized): Subscribe to HIF2
[ 17.019338] pfeng 46000000.pfe pfe2 (uninitialized): Host LLTX disabled
[ 17.019758] pfeng 46000000.pfe pfe2 (uninitialized): Enable HIF2
[ 17.019922] pfeng 46000000.pfe pfe2 (uninitialized): setting MAC addr: 00:04:9f:be:ef:02
[ 17.019950] pfeng 46000000.pfe pfe2 (uninitialized): PTP HW addend 0x80000000, max_adj configured to 46566128 ppb
[ 17.019958] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10.0ns
[ 17.020379] pfeng 46000000.pfe pfe2 (uninitialized): Registered PTP HW clock successfully on EMAC2
[ 17.021841] pfeng 46000000.pfe pfe2: registered
Then bringing up PFE2 and checking it with ethtool,
~ $ ifconfig pfe2 up
~ $ [ 232.134242] pfeng 46000000.pfe: HIF2 started
[ 232.134267] pfeng 46000000.pfe pfe2: configuring for fixed/sgmii link mode
[ 232.134638] pfeng 46000000.pfe pfe2: Link is Up - 1Gbps/Full - flow control off
[ 232.134880] IPv6: ADDRCONF(NETDEV_CHANGE): pfe2: link becomes ready
~ $ ethtool pfe2
Settings for pfe2:
Supported ports: [ MII ]
Supported link modes: 1000baseT/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 1000baseT/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Link partner advertised link modes: 1000baseT/Full
Link partner advertised pause frame use: No
Link partner advertised auto-negotiation: No
Link partner advertised FEC modes: Not reported
Speed: 1000Mb/s
Duplex: Full
Port: MII
PHYAD: 0
Transceiver: internal
Auto-negotiation: on
Link detected: yes
28 Replies
10-03-2024
12:15 PM
1,112 Views
minersrevolt
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Typo in question, I said MII-X when I meant SGMII.
The biggest concern I think is the XPCS init failure reporting from U-Boot.
10-03-2024
12:44 PM
1,111 Views
minersrevolt
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Also ifconfig output after attempting to ping the link partner (the link partner's ifconfig looks similar, tx only)
pfe2: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet 192.168.0.28 netmask 255.255.255.0 broadcast 192.168.0.255
inet6 fe80::204:9fff:febe:ef02 prefixlen 64 scopeid 0x20<link>
ether 00:04:9f:be:ef:02 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 32 bytes 2994 (2.9 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
device memory 0x46000000-46ffffff
10-03-2024
01:55 PM
1,107 Views
minersrevolt
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As another update we did confirm with a scope that we are seeing SGMII like data on the TX/RX pins to the PHY after we enabled the PHY (ifconfig pfe2 up). Scope is only 1 GHz so not high enough resolution to interpret the data but it was present following bringing the PHY up.
10-04-2024
12:57 PM
1,051 Views
minersrevolt
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Definitely looks like it isn't being initialized correctly,
=> xpcs list
Registered XPCS instances:
| ID | SerDes instance | XPCS |
| 0 | serdes@40480000 | 1 |
=> xpcs 0 dump
0x001f0000 => 0x8004
0x001f0001 => 0x8004
0x001f0002 => 0x8004
0x001f0003 => 0x8004
0x001f0004 => 0x8004
0x001f0005 => 0x8004
0x001f0006 => 0x8004
0x001f000f => 0x8004
0x001f0708 => 0x8004
0x001f0709 => 0x8004
0x001f070a => 0x8004
0x001f070b => 0x8004
0x001f070c => 0x8004
0x001f070d => 0x8004
0x001f070e => 0x8004
0x001f070f => 0x8004
0x001f0710 => 0x8004
0x001f8000 => 0x8004
0x001f8001 => 0x8004
0x001f8002 => 0x8004
0x001f8003 => 0x8004
0x001f8005 => 0x8004
0x001f800a => 0x8004
0x001f8010 => 0x8004
0x001f8011 => 0x8004
0x001f8012 => 0x8004
0x001f8015 => 0x8004
0x001f8018 => 0x8004
0x001f8020 => 0x8004
0x001f8030 => 0x8004
0x001f8031 => 0x8004
0x001f8032 => 0x8004
0x001f8033 => 0x8004
0x001f8034 => 0x8004
0x001f8035 => 0x8004
0x001f8036 => 0x8004
0x001f8037 => 0x8004
0x001f803c => 0x8004
0x001f8040 => 0x8004
0x001f8050 => 0x8004
0x001f8051 => 0x8004
0x001f8052 => 0x8004
0x001f8053 => 0x8004
0x001f8054 => 0x8004
0x001f8055 => 0x8004
0x001f8056 => 0x8004
0x001f8057 => 0x8004
0x001f8058 => 0x8004
0x001f805c => 0x8004
0x001f805d => 0x8004
0x001f805e => 0x8004
0x001f8060 => 0x8004
0x001f8064 => 0x8004
0x001f806b => 0x8004
0x001f8070 => 0x8004
0x001f8071 => 0x8004
0x001f8072 => 0x8004
0x001f8073 => 0x8004
0x001f8074 => 0x8004
0x001f8075 => 0x8004
0x001f8076 => 0x8004
0x001f8077 => 0x8004
0x001f8078 => 0x8004
0x001f8090 => 0x8004
0x001f8091 => 0x8004
0x001f8092 => 0x8004
0x001f8096 => 0x8004
0x001f8098 => 0x8004
0x001f8099 => 0x8004
0x001f809a => 0x8004
0x001f809b => 0x0000
0x001f809c => 0x8004
0x001f809d => 0x8004
10-08-2024
12:54 PM
975 Views
minersrevolt
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Enabling the PFE phys in the AT-F device tree now shows the registers and they look correct but still cannot ping on the interface. I also get a crash when attempting to boot into Linux from this mode (doesn't happen in the others),
U-boot,
OVERRIDE: xpcs0_1 and xpcs 1_0 can't be both SGMII
In: serial@401c8000
Out: serial@401c8000
Err: serial@401c8000
Board revision: RDB3
Net:
Found PFE version 0x0101 (S32G3)
pfeng pfeng-base: Uploading CLASS firmware
pfeng pfeng-base: EMAC0 not used, skipped
pfeng pfeng-base: EMAC1 not used, skipped
pfeng pfeng-base: EMAC2 block was initialized
pfeng pfeng-base: Enabling the CLASS block
pfeng pfeng-base: PFE Platform started successfully (mask: 4)
s32cc_serdes_phy serdes@40480000: Using mode 3 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: INT Clock selected
s32cc_serdes_phy serdes@40480000: INT Clock selected
s32cc_serdes_phy serdes@40480000: Unstable RX detected on XPCS1
s32cc_serdes_phy serdes@40480000: Unstable RX detected on XPCS0
eth3: pfe2
=> xpcs 0 dump [40/4796]
0x001f0000 => 0x0140
0x001f0001 => 0x0189
0x001f0002 => 0x7996
0x001f0003 => 0xced0
0x001f0004 => 0x0020
0x001f0005 => 0x0000
0x001f0006 => 0x0000
0x001f000f => 0xc000
0x001f0708 => 0x0003
Device Tree, only using PFE2 for now the others are status = "disabled".
pfe: pfe@46000000 {
compatible = "nxp,s32g-pfe"; reg = <0x0 0x46000000 0x0 0x1000000>,
<0x0 0x4007ca00 0x0 0x100>; reg-names = "pfe-cbus", "s32g-main-gpr";
#address-cells = <1>; #size-cells = <0>; resets = <&reset S32CC_SCMI_RST_PART2>; reset-names = "pfe_part";
clocks = <&clks S32G_SCMI_CLK_PFE_AXI>, <&clks S32G_SCMI_CLK_PFE_PE>;
clock-names = "pfe_sys", "pfe_pe";
nvmem-cells = <&pfe_emacs_intf_sel>, <&pfe_coh_en>,
<&pfe_pwr_ctrl>, <&pfe_emacs_genctrl1>;
nvmem-cell-names = "pfe_emacs_intf_sel", "pfe_coh_en",
"pfe_pwr_ctrl", "pfe_emacs_genctrl1";
phys = <&serdes1 PHY_TYPE_XPCS 0 0>,
<&serdes1 PHY_TYPE_XPCS 1 1>,
<&serdes0 PHY_TYPE_XPCS 1 1>;
phy-names = "emac0_xpcs", "emac1_xpcs", "emac2_xpcs"; dma-coherent;
memory-region = <&pfe_reserved>;
status = "okay";
/* MDIO on EMAC 2 */
pfe_mdio2: mdio@2 {
compatible = "nxp,s32g-pfe-mdio";
reg = <2>;
pfe_mdiob_phy2: ethernet-phy@0 {
reg = <0>;
/* ti,op-mode = <DP83869_SGMII_COPPER_ETHERNET>; */
};
};
/* PFE2 */
pfe_netif2: ethernet@3 {
compatible = "nxp,s32g-pfe-netif";
status = "okay";
reg = <3>;
local-mac-address = [ 00 04 9F BE EF 02 ];
nxp,pfeng-if-name = "pfe2";
nxp,pfeng-hif-channels = <PFE_HIF_CHANNEL_2>;
nxp,pfeng-linked-phyif = <PFE_PHYIF_EMAC_2>;
clocks = <&clks S32G_SCMI_CLK_PFE2_TX_SGMII>,
<&clks S32G_SCMI_CLK_PFE2_TX_RGMII>,
<&clks S32G_SCMI_CLK_PFE2_TX_RMII>,
<&clks S32G_SCMI_CLK_PFE2_TX_MII>,
<&clks S32G_SCMI_CLK_PFE2_RX_SGMII>,
<&clks S32G_SCMI_CLK_PFE2_RX_RGMII>,
<&clks S32G_SCMI_CLK_PFE2_RX_RMII>,
<&clks S32G_SCMI_CLK_PFE2_RX_MII>;
clock-names = "tx_sgmii", "tx_rgmii",
"tx_rmii", "tx_mii",
"rx_sgmii", "rx_rgmii",
"rx_rmii", "rx_mii";
phy-mode = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
Kernel Panic,
Starting kernel ...
"Synchronous Abort" handler, esr 0x96000210
elr: 00000000ff8e1520 lr : 00000000ff8e151c (reloc)
elr: 00000000ff8e1520 lr : 00000000ff8e151c
x0 : 0000000000000000 x1 : 00000000ffffffff
x2 : 0000000000000007 x3 : 00000000ff929a08
x4 : 0000000000000003 x5 : 0000000000000014
x6 : 0000000000000000 x7 : 00000000ffc23e40
x8 : 000000008300b000 x9 : 0000000000000002
x10: 0000000083000000 x11: 000000008300dbe1
x12: 0000000000000000 x13: 000000008300afff
x14: 0000000083000000 x15: 0000000000000000
x16: 00000000ff920ed4 x17: 0000000000000000
x18: 00000000ffbcfd80 x19: 00000000ffc1d2c0
x20: 00000000ffbf9150 x21: 00000000ffbf9138
x22: 00000000ff94fe68 x23: 0000000000004600
x24: 00000000ffffff7f x25: 0000000000000000
x26: 0000000000000400 x27: 00000000ff8a292c
x28: 0000000000000000 x29: 00000000ffbc5830
Code: 9100a294 91014260 9400090b f94002a0 (f9400001)
Resetting CPU ...
10-08-2024
02:38 PM
958 Views
minersrevolt
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Doing some testing on the RDB3 board for comparison and really the only difference I can find is that the SERDES is not initializing in ours while it is in the RDB3. The problem has to be with the SERDES block being held in reset and/or failing initialization. What would cause this based on the u-boot settings shown in previous posts?
10-09-2024
01:24 PM
905 Views
alejandro_e
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Hello @minersrevolt,
I'm really sorry for the late reply, the team's bandwidth is quite limited at the moment.
About your problem, I tested with the hwconfig you mentioned and I was not able to ping other devices through PFE2 using the RDB3. Can you test using the following configuration? these steps are for configuring u-boot trough the command line:
=> setenv hwconfig "serdes0:mode=pcie,clock=ext;pcie0:mode=rc;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=1G;xpcs1_1:speed=1G"
=> setenv ethact pfe2
=> setenv autoload no
=> saveenv
After this, please reboot your board and configure the IP:
=> setenv ipaddr X.X.X.X
Where X.X.X.X is the IP to assign to your board, it should be in the same network segment of the device you want to ping.
You can also get an IP assigned by executing:
=> dhcp
BOOTP broadcast 1
DHCP client bound to address W.W.W.W (200 ms)
where W.W.W.W is the IP that your DHCP server will assign to your board.
after getting a valid IP assigned you will be able to ping other devices, for example your computer:
=> ping Y.Y.Y.Y
Using pfe2 device
host Y.Y.Y.Y is alive
Where Y.Y.Y.Y is the IP of the device that is already connected to the network.
for example, I used the DHCP IP assignment and i did ping on my windows computer (this is after the hwconfig and etchact configuration):
NOTICE: Reset status: Error
NOTICE: BL2: v2.5(release):bsp40.0_rc9-2.5
NOTICE: BL2: Built : 08:41:20, Mar 21 2024
NOTICE: BL2: Booting BL31
U-Boot 2022.04+gd482def7e3+p0 (Mar 21 2024 - 08:40:56 +0000)
SoC: NXP S32G399A rev. 1.1
CPU: ARM Cortex-A53 r0p4 @ max 1300 MHz
Model: NXP S32G399A-RDB3
DRAM: 3.5 GiB
Core: 306 devices, 25 uclasses, devicetree: board
MMC: FSL_SDHC: 0
Loading Environment from MMC... OK
s32cc_serdes_phy serdes@40480000: Using mode 0 for SerDes subsystem
pci_s32cc pcie@40400000: Configuring as RootComplex
pci_s32cc pcie@40400000: Failed to get link up
In: serial@401c8000
Out: serial@401c8000
Err: serial@401c8000
Board revision: RDB3 Revision F
PCIe: BusDevFun VendorId DeviceId Device Class Sub-Class
__________________________________________________________________________
pcie@40400000 RootComplex
| `-- 01:00.00 0x1957 0x4300 Bridge device 0x04
Net: eth0: ethernet@4033c000
Found PFE version 0x0101 (S32G3)
pfeng pfeng-base: Uploading CLASS firmware
pfeng pfeng-base: EMAC0 block was initialized
pfeng pfeng-base: EMAC1 block was initialized
pfeng pfeng-base: EMAC2 block was initialized
pfeng pfeng-base: Enabling the CLASS block
pfeng pfeng-base: PFE Platform started successfully (mask: 7)
s32cc_serdes_phy serdes@44180000: Using mode 3 for SerDes subsystem
s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS1
s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS0
, eth1: pfe0, eth2: pfe1, eth3: pfe2
Hit any key to stop autoboot: 0
=>
=> dhcp
pfe2 Waiting for PHY auto negotiation to complete....... done
BOOTP broadcast 1
BOOTP broadcast 2
DHCP client bound to address 172.16.103.120 (454 ms)
=> ping 172.16.105.157
Using pfe2 device
host 172.16.105.157 is alive
=>
You can also see from the boot logs that I don't have errors while u-boot is configuring the SerDes instances.
I am using the P3B connector:
Let me know if this information solves your problem.
10-09-2024
01:32 PM
903 Views
minersrevolt
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Hey @alejandro_e thanks for the reply. I would like to try that but one of the problems we have is we have to use PFE2 attached to SERDES0 Lane 1 @ 1.25Gbps which is mode 1/2/3 seen below. This is the only PFE PHY we currently have available on the board.
Given that constraint I can't follow your instructions unfortunately since you are setting SERDES0 in PCIe mode.
10-09-2024
01:51 PM
897 Views
alejandro_e
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Hello @minersrevolt,
Which pins of the S32G3 are you connecting your DP83869 PHY? in the RDB3 the pins used for the P3B are the following:
are you using the same pins?
Thanks for the information in advance.
10-09-2024
02:03 PM
893 Views
minersrevolt
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@alejandro_e No they're not the same, we are using the SGMII mode. SGMII0_TX/RX are tied to the PHY. We have the MDIO bus working to the PHY so it is just the data lanes.
10-09-2024
03:19 PM
857 Views
alejandro_e
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Hello @minersrevolt,
Sorry for the confusion, can you try the steps I mentioned above but with the following configuration:
"serdes0:mode=pcie&xpcs1,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G,an=0;serdes1:mode=disable"
I am not able to test if this really works because the RDB3 HW uses the PCIe lanes differently.
all I can see is that u-boot accepts the configuration as valid:
NOTICE: Reset status: Power-On Reset
NOTICE: BL2: v2.5(release):bsp40.0_rc9-2.5
NOTICE: BL2: Built : 08:41:20, Mar 21 2024
NOTICE: BL2: Booting BL31
U-Boot 2022.04+gd482def7e3+p0 (Mar 21 2024 - 08:40:56 +0000)
SoC: NXP S32G399A rev. 1.1
CPU: ARM Cortex-A53 r0p4 @ max 1300 MHz
Model: NXP S32G399A-RDB3
DRAM: 3.5 GiB
Core: 306 devices, 25 uclasses, devicetree: board
MMC: FSL_SDHC: 0
Loading Environment from MMC... OK
Disabling XPCS1_0
Disabling XPCS1_1
s32cc_serdes_phy serdes@40480000: Using mode 2 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: Unstable RX detected on XPCS1
pci_s32cc pcie@40400000: Configuring as RootComplex
pci_s32cc pcie@40400000: Failed to get link up
In: serial@401c8000
Out: serial@401c8000
Err: serial@401c8000
Board revision: RDB3 Revision F
PCIe: BusDevFun VendorId DeviceId Device Class Sub-Class
__________________________________________________________________________
pcie@40400000 RootComplex
| `-- 01:00.00 0x1957 0x4300 Bridge device 0x04
Net: eth0: ethernet@4033c000
Found PFE version 0x0101 (S32G3)
pfeng pfeng-base: Uploading CLASS firmware
pfeng pfeng-base: EMAC0 not used, skipped
pfeng pfeng-base: EMAC1 not used, skipped
pfeng pfeng-base: EMAC2 block was initialized
pfeng pfeng-base: Enabling the CLASS block
pfeng pfeng-base: PFE Platform started successfully (mask: 4)
, eth3: pfe2
Hit any key to stop autoboot: 0
=>
=> printenv hwconfig
hwconfig=serdes0:mode=pcie&xpcs1,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G,an=0;serdes1:mode=disable
=> xpcs list
Registered XPCS instances:
| ID | SerDes instance | XPCS |
| 0 | serdes@40480000 | 1 |
=>
as you can see the SerDes mode is 2 and the XPCS active instance is the SerDes0, you can double check that in the device tree [fdts\s32cc.dtsi]:
Let me know if this information solved your problem.
10-09-2024
03:57 PM
853 Views
minersrevolt
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Hey @alejandro_e
Okay that makes sense but I'm still getting initialization errors which is odd. I am using the imported device tree from the AT-F but I don't see why that would cause issues, the changes are being clearly reflected in U-boot. Here is what I'm currently seeing with those settings. Note I am not loading the pfeng module in U-Boot because that was causing me Linux boot issues which is probably unrelated, but since it fails to initialize before that step I'm not sure it really matters here.
U-Boot 2022.04-g591ddcc56c-dirty (Oct 09 2024 - 15:28:59 -0700)
SoC: NXP S32G399A rev. 1.1
CPU: ARM Cortex-A53 r0p4 @ max 1300 MHz
Model: S32G399A
DRAM: 4 GiB
Core: 304 devices, 25 uclasses, devicetree: board
MMC: FSL_SDHC: 0
Loading Environment from SPIFlash... SF: Detected mt35xu02gcba with page size 256 Bytes, erase size 4 KiB, total 255.9 MiB
*** Warning - bad CRC, using default environment
Failed to configure XPCS0_1
Failed to update XPCS1 for SerDes0
Disabling XPCS1_0
Disabling XPCS1_1
s32cc_serdes_phy serdes@40480000: Using mode 2 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: INT Clock selected
s32cc_serdes_phy serdes@40480000: XPCS1 is in reset
s32cc_serdes_phy serdes@40480000: XPCS init failed
pci_s32cc pcie@40400000: Failed to get PHY 'serdes_lane0'
In: serial@401c8000
Out: serial@401c8000
Err: serial@401c8000
Board revision: RDB3
Net:
Found PFE version 0x0101 (S32G3)
PFEng firmware file 'mmc@0:1:s32g_pfe_class.fw' loading failed: -2
No ethernet found.
Hit any key to stop autoboot: 0
=> printenv hwconfig
hwconfig=serdes0:mode=pcie&xpcs1,clock=int,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G,an=1;serdes1:mode=disable
=> xpcs list
Registered XPCS instances:
| ID | SerDes instance | XPCS |
| 0 | serdes@40480000 | 1 |The serdes0 dtsi entry matches yours in s32cc.dtsi,
serdes0: serdes@40480000 {
#phy-cells = <3>;
compatible = "nxp,s32cc-serdes";
clocks = <&clks S32CC_SCMI_CLK_SERDES_AXI>,
<&clks S32CC_SCMI_CLK_SERDES_AUX>,
<&clks S32CC_SCMI_CLK_SERDES_APB>,
<&clks S32CC_SCMI_CLK_SERDES_REF>;
clock-names = "axi", "aux", "apb", "ref";
#address-cells = <3>;
#size-cells = <2>;
num-lanes = <2>; /* supports max 2 lanes */
resets = <&reset S32CC_SCMI_RST_SERDES0>,
<&reset S32CC_SCMI_RST_PCIE0>;
reset-names = "serdes", "pcie";
reg = <0x0 0x40480000 0x0 0x108>,
<0x0 0x40483008 0x0 0x10>,
<0x0 0x40482000 0x0 0x800>,
<0x0 0x40482800 0x0 0x800>;
reg-names = "ss_pcie", "pcie_phy", "xpcs0", "xpcs1";
status = "okay";
};
I'm wondering if it has something to do with the clocking since I am using the internally generated clock instead of the external one? Is that possible to verify on your side?
10-10-2024
08:49 AM
814 Views
alejandro_e
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Hello @minersrevolt,
About the loading of s32g_pfe_class.fw, although you need it once you try to ping any IP using pfe2 it should not be related to the initialization errors you are getting for XPCS.
I tried the configuration you shared and I did not get the initialization errors you are getting:
NOTICE: Reset status: Power-On Reset
NOTICE: BL2: v2.5(release):bsp40.0_rc9-2.5
NOTICE: BL2: Built : 08:41:20, Mar 21 2024
NOTICE: BL2: Booting BL31
U-Boot 2022.04+gd482def7e3+p0 (Mar 21 2024 - 08:40:56 +0000)
SoC: NXP S32G399A rev. 1.1
CPU: ARM Cortex-A53 r0p4 @ max 1300 MHz
Model: NXP S32G399A-RDB3
DRAM: 3.5 GiB
Core: 306 devices, 25 uclasses, devicetree: board
MMC: FSL_SDHC: 0
Loading Environment from MMC... OK
Disabling XPCS1_0
Disabling XPCS1_1
s32cc_serdes_phy serdes@40480000: Using mode 2 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: Unstable RX detected on XPCS1
pci_s32cc pcie@40400000: Configuring as RootComplex
pci_s32cc pcie@40400000: Failed to get link up
In: serial@401c8000
Out: serial@401c8000
Err: serial@401c8000
Board revision: RDB3 Revision F
PCIe: BusDevFun VendorId DeviceId Device Class Sub-Class
__________________________________________________________________________
pcie@40400000 RootComplex
| `-- 01:00.00 0x1957 0x4300 Bridge device 0x04
Net: eth0: ethernet@4033c000
Found PFE version 0x0101 (S32G3)
PFEng firmware file 'mmc@0:1:s32g_pfe_class.fw' loading failed: -2
Hit any key to stop autoboot: 0
=>
=> printenv hwconfig
hwconfig=serdes0:mode=pcie&xpcs1,clock=int,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G,an=1;serdes1:mode=disable
=> xpcs list
Registered XPCS instances:
| ID | SerDes instance | XPCS |
| 0 | serdes@40480000 | 1 |
=>
The only difference in the device tree node is the following, your node is on the left:
which should no be interfering with the behavior of the device.
Other than the override you did to have xpcs0_1 and xpcs 1_0 both in SGMII, did you change something else on the serdes drivers?
Thanks in advance for the information.
10-11-2024
09:03 AM
772 Views
minersrevolt
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That is concerning.
I didn't change anything else in the SERDES drivers and I've tried with and without the override modification to the same effect. Strangely enough I do see SERDES1 not presenting this behavior when booting however I don't see anything listed in xpcs list in U-boot.
U-Boot 2022.04-g3b93c9058d (Oct 10 2024 - 15:29:34 -0700)
SoC: NXP S32G399A rev. 1.1
CPU: ARM Cortex-A53 r0p4 @ max 1300 MHz
Model: S32G399A
DRAM: 4 GiB
Core: 304 devices, 25 uclasses, devicetree: board
MMC: FSL_SDHC: 0
Loading Environment from SPIFlash... SF: Detected mt35xu02gcba with page size 256 Bytes, erase size 4 KiB, total 255.9 MiB
*** Warning - bad CRC, using default environment
s32cc_serdes_phy serdes@40480000: Using mode 0 for SerDes subsystem
pci_s32cc pcie@40400000: DBI R/W is not being enabled
pci_s32cc pcie@40400000: PCI Device and Vendor IDs could not be set
pci_s32cc pcie@40400000: DBI R/W is not being enabled
s32cc_serdes_phy serdes@40480000: INT Clock selected
pci_s32cc pcie@40400000: Configuring as RootComplex
pci_s32cc pcie@40400000: Failed to get link up
In: serial@401c8000
Out: serial@401c8000
Err: serial@401c8000
Board revision: RDB3
PCIe: BusDevFun VendorId DeviceId Device Class Sub-Class
__________________________________________________________________________
pcie@40400000 RootComplex
| `-- 01:00.00 0x16c3 0x4300 Bridge device 0x04
Net:
Found PFE version 0x0101 (S32G3)
PFEng firmware file 'mmc@0:1:s32g_pfe_class.fw' loading failed: -2
Found PFE version 0x0101 (S32G3)
PFEng firmware file 'mmc@0:1:s32g_pfe_class.fw' loading failed: -2
Found PFE version 0x0101 (S32G3)
PFEng firmware file 'mmc@0:1:s32g_pfe_class.fw' loading failed: -2
No ethernet found.
Hit any key to stop autoboot: 0
=> printenv hwconfig
hwconfig=serdes0:pcie,clock=int,fmhz=100;pcie0:mode=rc;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=100;xpcs1_0:speed=1G,an=0;xpcs1_1:speed=1G,an=0
=> xpcs list
Registered XPCS instances:
| ID | SerDes instance | XPCS |and from Linux,
[ 1.139504] phy-s32cc-serdes 40480000.serdes: Using mode 0 for SerDes subsystem
[ 1.139835] phy-s32cc-serdes 44180000.serdes: Using mode 3 for SerDes subsystem
[ 1.145946] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS1
[ 1.145965] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS0
10-11-2024
12:33 PM
738 Views
minersrevolt
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Looks like the only reason I didn't get the XPCS failure/init messages was because I had the pfe_netif set to "disabled" in the device tree for the AT-F/U-Boot. Bringing it back to "okay" brought back the initialization failures in u-boot.
10-11-2024
12:43 PM
733 Views
alejandro_e
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Hello @minersrevolt,
I tested the last hwconfig you sent with and without the s32g_pfe_class.fw and I see two very different behaviors:
With s32g_pfe_class.fw:
U-Boot 2022.04+gd482def7e3+p0 (Mar 21 2024 - 08:40:56 +0000)
SoC: NXP S32G399A rev. 1.1
CPU: ARM Cortex-A53 r0p4 @ max 1300 MHz
Model: NXP S32G399A-RDB3
DRAM: 3.5 GiB
Core: 306 devices, 25 uclasses, devicetree: board
MMC: FSL_SDHC: 0
Loading Environment from MMC... OK
s32cc_serdes_phy serdes@40480000: Using mode 0 for SerDes subsystem
pci_s32cc pcie@40400000: Configuring as RootComplex
pci_s32cc pcie@40400000: Failed to get link up
In: serial@401c8000
Out: serial@401c8000
Err: serial@401c8000
Board revision: RDB3 Revision F
PCIe: BusDevFun VendorId DeviceId Device Class Sub-Class
__________________________________________________________________________
pcie@40400000 RootComplex
| `-- 01:00.00 0x1957 0x4300 Bridge device 0x04
Net: eth0: ethernet@4033c000
Found PFE version 0x0101 (S32G3)
pfeng pfeng-base: Uploading CLASS firmware
pfeng pfeng-base: EMAC0 block was initialized
pfeng pfeng-base: EMAC1 block was initialized
pfeng pfeng-base: EMAC2 block was initialized
pfeng pfeng-base: Enabling the CLASS block
pfeng pfeng-base: PFE Platform started successfully (mask: 7)
s32cc_serdes_phy serdes@44180000: Using mode 3 for SerDes subsystem
s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS1
s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS0
, eth1: pfe0, eth2: pfe1, eth3: pfe2
Hit any key to stop autoboot: 0
=>
=> printenv hwconfig
hwconfig=serdes0:pcie,clock=int,fmhz=100;pcie0:mode=rc;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=100;xpcs1_0:speed=1G,an=0;xpcs1_1:speed=1G,an=0
=> xpcs list
Registered XPCS instances:
| ID | SerDes instance | XPCS |
| 0 | serdes@44180000 | 1 |
| 1 | serdes@44180000 | 0 |
=>
Without s32g_pfe_class.fw:
U-Boot 2022.04+gd482def7e3+p0 (Mar 21 2024 - 08:40:56 +0000)
SoC: NXP S32G399A rev. 1.1
CPU: ARM Cortex-A53 r0p4 @ max 1300 MHz
Model: NXP S32G399A-RDB3
DRAM: 3.5 GiB
Core: 306 devices, 25 uclasses, devicetree: board
MMC: FSL_SDHC: 0
Loading Environment from MMC... OK
s32cc_serdes_phy serdes@40480000: Using mode 0 for SerDes subsystem
pci_s32cc pcie@40400000: Configuring as RootComplex
pci_s32cc pcie@40400000: Failed to get link up
In: serial@401c8000
Out: serial@401c8000
Err: serial@401c8000
Board revision: RDB3 Revision F
PCIe: BusDevFun VendorId DeviceId Device Class Sub-Class
__________________________________________________________________________
pcie@40400000 RootComplex
| `-- 01:00.00 0x1957 0x4300 Bridge device 0x04
Net: eth0: ethernet@4033c000
Found PFE version 0x0101 (S32G3)
PFEng firmware file 'mmc@0:1:s32g_pfe_class.fw' loading failed: -2
Found PFE version 0x0101 (S32G3)
PFEng firmware file 'mmc@0:1:s32g_pfe_class.fw' loading failed: -2
Found PFE version 0x0101 (S32G3)
PFEng firmware file 'mmc@0:1:s32g_pfe_class.fw' loading failed: -2
Hit any key to stop autoboot: 0
=>
=> printenv hwconfig
hwconfig=serdes0:pcie,clock=int,fmhz=100;pcie0:mode=rc;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=100;xpcs1_0:speed=1G,an=0;xpcs1_1:speed=1G,an=0
=> xpcs list
Registered XPCS instances:
| ID | SerDes instance | XPCS |
=>
As you can see I can only get the XPCS listed when using the s32g_pfe_class.fw. Could you please try adding the s32g_pfe_class.fw to have a more similar setup?
As for the linux side, I see the same messages:
[ 1.176872] phy-s32cc-serdes 40480000.serdes: Using mode 0 for SerDes subsystem
[ 1.177199] phy-s32cc-serdes 44180000.serdes: Using mode 3 for SerDes subsystem
[ 1.183312] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS1
[ 1.183330] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS0
About the initialization issues in u-boot, I am now worried about this part of your logs
*** Warning - bad CRC, using default environment
Could you share the output of the printenv command? without any parameters, it should look something like this:
=> printenv
baudrate=115200
board_rev=F
boot_mtd=booti
bootargs=root=/dev/ram rw earlycon loglevel=7
bootcmd=mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; fi; fi
bootdelay=2
console=ttyLF0
eth1addr=00:04:9f:be:ef:00
eth2addr=00:04:9f:be:ef:01
eth3addr=00:04:9f:be:ef:02
ethaddr=96:28:9e:45:2b:c6
fdt_addr=0x83000000
fdt_enable_hs400es=fdt addr ${fdt_addr}; fdt rm /soc/mmc no-1-8-v; fdt resize;
fdt_file=s32g399a-rdb3.dtb
fdt_high=0xffffffffffffffff
fdt_override=;
fdtcontroladdr=ff895000
flashboot=echo Booting from flash...; run flashbootargs;mtd read Kernel ${loadaddr};mtd read DTB ${fdt_addr};mtd read Rootfs ${ramdisk_addr};${boot_mtd} ${loadaddr} ${ramdisk_addr} ${fdt_addr};
flashbootargs=setenv bootargs console=${console},${baudrate} root=/dev/ram rw earlycon ;setenv flashsize 0x04000000;
hwconfig=serdes0:pcie,clock=int,fmhz=100;pcie0:mode=rc;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=100;xpcs1_0:speed=1G,an=0;xpcs1_1:speed=1G,an=0
image=Image
initrd_high=0xffffffffffffffff
ipaddr=10.0.0.100
loadaddr=0x80000000
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}; run fdt_override;
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
loadtftpfdt=tftp ${fdt_addr} ${fdt_file};
loadtftpimage=tftp ${loadaddr} ${image};
mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon
mmcboot=echo Booting from mmc ...; run mmcargs; if run loadfdt; then run fdt_fixups; ${boot_mtd} ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi;
mmcdev=0
mmcpart=1
mmcroot=/dev/mmcblk0p2 rootwait rw
netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp earlycon
netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${image}; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if ${get_cmd} ${fdt_addr} ${fdt_file}; then ${boot_mtd} ${loadaddr} - ${fdt_addr}; else if test ${boot_fdt} = try; then ${boot_mtd}; else echo WARN: Cannot load the DT; fi; fi; else ${boot_mtd}; fi;
netmask=255.255.255.0
nfsboot=echo Booting from net using tftp and nfs...; run nfsbootargs;run loadtftpimage; run loadtftpfdt;${boot_mtd} ${loadaddr} - ${fdt_addr};
nfsbootargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs rw ip=${ipaddr}:${serverip}::${netmask}::eth0:off nfsroot=${serverip}:/tftpboot/rfs,nolock,v3,tcp earlycon
pfe1_phy_addr=8
ramdisk_addr=0x90000000
script=boot.scr
serverip=10.0.0.1
stderr=serial@401c8000
stdin=serial@401c8000
stdout=serial@401c8000
Environment size: 2589/8188 bytes
=>
Thanks in advance for the information.
a month ago
632 Views
minersrevolt
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Hey @alejandro_e ,
The crc error message is unrelated, it has to do with trying to store the uEnv to a raw NOR flash on the QSPI that isn't quite cooperating, not concerned with it for this particular issue. To be clear we are currently running the FIP on an SD card.
We saw a similar output with respect to the ``xpcs list`` functionality depending on whether the pfe firmware is preset or not.
Still mainly concerned about the XPCS0_1 failure to initialize and pull itself out of reset.
Here's the output of printenv,
=> printenv
baudrate=115200
boot_mtd=booti
bootargs=root=/dev/ram rw earlycon loglevel=7
bootcmd=mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; fi; fi
bootdelay=2
console=ttyLF0
fdt_addr=0x83000000
fdt_enable_hs400es=fdt addr ${fdt_addr}; fdt rm /soc/mmc no-1-8-v; fdt resize;
fdt_file=s32g399a-rdb3.dtb
fdt_high=0xffffffffffffffff
fdt_override=;
fdtcontroladdr=ff895000
flashboot=echo Booting from flash...; run flashbootargs;mtd read Kernel ${loadaddr};mtd read DTB ${fdt_addr};mtd read Rootfs ${ramdisk_addr};${boot_mtd} ${loadaddr} ${ramdisk_addr} ${fdt_addr};
flashbootargs=setenv bootargs console=${console},${baudrate} root=/dev/ram rw earlycon ;setenv flashsize 0x04000000;
hwconfig=serdes0:mode=pcie&xpcs1,clock=int,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G;serdes1:mode=disable
image=Image
initrd_high=0xffffffffffffffff
ipaddr=10.0.0.100
loadaddr=0x80000000
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}; run fdt_override;
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
loadtftpfdt=tftp ${fdt_addr} ${fdt_file};
loadtftpimage=tftp ${loadaddr} ${image};
mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon
mmcboot=echo Booting from mmc ...; run mmcargs; if run loadfdt; then run fdt_fixups; ${boot_mtd} ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi;
mmcdev=0
mmcpart=1
mmcroot=/dev/mmcblk0p2 rootwait rw
netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp earlycon
netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${image}; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if ${get_cmd} ${fdt_addr} ${fdt_file}; then ${boot_mtd} ${loadaddr} - ${fdt_addr}; else if test ${boot_fdt} = try; then ${boot_mtd}; else echo WARN: Cannot load th;
netmask=255.255.255.0
nfsboot=echo Booting from net using tftp and nfs...; run nfsbootargs;run loadtftpimage; run loadtftpfdt;${boot_mtd} ${loadaddr} - ${fdt_addr};
nfsbootargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs rw ip=${ipaddr}:${serverip}::${netmask}::eth0:off nfsroot=${serverip}:/tftpboot/rfs,nolock,v3,tcp earlycon
ramdisk_addr=0x90000000
script=boot.scr
serverip=10.0.0.1
stderr=serial@401c8000
stdin=serial@401c8000
stdout=serial@401c8000
a month ago
605 Views
alejandro_e
NXP TechSupport
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hello @minersrevolt,
My concern about the CRC message is because if the u-env is loaded as default, the changes in hwconfig will no be visible because it needs a reboot to take effect, if you are sure your u-env is being correctly loaded then that should not be a problem.
After a lot of investigation I might have found a solution to the problem, the only issue is that I used the 2.5G configuration since with the RDB3 changing to the 1G configuration requires changes in other ICs (before I said that I was not able to test PFE in PCIe configuration, I misunderstood the schematics, those signals are multiplexed in a very complex array of muxes I apologize for that).
I was able to ping my windows PC using PFE2 in mode 2 and 3:
mode 2:
serdes0:mode=pcie&xpcs1,clock=int,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=2G5,an=0;serdes1:mode=disable
mode 3:
hwconfig=serdes0:mode=xpcs0&xpcs1,clock=int,fmhz=100;xpcs0_1:speed=2G5,an=0;serdes1:mode=disable
in theory to use 1G speed you can use:
mode 2:
serdes0:mode=pcie&xpcs1,clock=int,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G,an=0;serdes1:mode=disable
mode 3:
serdes0:mode=xpcs0&xpcs1,clock=int,fmhz=100;xpcs0_0:speed=1G,an=0;xpcs0_1:speed=1G,an=0;serdes1:mode=disable
if the problem with XPCS0_1 persist please use the verifclk and share the output with me so I may analyze if the problem is related to the clock configuration, the output should look something like this:
=> verifclk
CMU | Monitored | Reference | Expected | Verified
ID | clock | clock | range (MHz) | range (MHz)
-----|--------------|-----------|---------------------|--------------------
0| FXOSC | FIRC | 40.000 | 39.062
1| FIRC | FXOSC | 45.600 - 50.400 | 48.144
2| SIRC | FXOSC | 0.032 | 0.031
Timeout while measuring the frequency of FTM_0_REF
3| FTM_0_REF | FXOSC | 40.000 | 0.000
Timeout while measuring the frequency of FTM_1_REF
4| FTM_1_REF | FXOSC | 40.000 | 0.000
5| XBAR_DIV3 | FIRC | 133.333 | 125.000
6| XBAR_M7_0 | FIRC | 400.000 | 375.000
7| XBAR_DIV3 | FXOSC | 133.333 | 132.812
8| XBAR_M7_1 | FIRC | 400.000 | 375.000
9| XBAR_M7_2 | FIRC | 400.000 | 375.000
24| XBAR_M7_3 | FIRC | 400.000 | 375.000
10| PER | FIRC | 80.000 | 78.125
11| SERDES_REF | FXOSC | 100.000 - 125.000 | 99.609
12| FLEXRAY_PE | FXOSC | 40.000 | 0.000 - 0.015
13| CAN_PE | FXOSC | 80.000 | 47.851
14| GMAC_0_TX | FXOSC | 2.500 - 125.000 | 125.000
15| GMAC_TS | FXOSC | 5.000 - 200.000 | 0.000 - 0.015
16| LIN | FXOSC | 125.000 | 62.500
17| QSPI_1X | FXOSC | 0.000 - 200.000 | 0.000 - 0.015
18| SDHC | FXOSC | 400.000 | 398.437
20| DDR | FIRC | 800.000 | 812.500
21| GMAC_0_RX | FXOSC | 2.500 - 125.000 | 24.902
22| SPI | FXOSC | 100.000 | 47.851
27| A53_CORE | FXOSC | 1300.000 | 1312.500
28| A53_CORE | FIRC | 1300.000 | 1250.000
39| PFE_SYS | FXOSC | 300.000 | 300.781
46| PFE_MAC_0_TX | FXOSC | 2.500 - 312.500 | 0.000 - 0.015
47| PFE_MAC_0_RX | FXOSC | 2.500 - 312.500 | 47.851
48| PFE_MAC_1_TX | FXOSC | 2.500 - 312.500 | 0.000 - 0.015
49| PFE_MAC_1_RX | FXOSC | 2.500 - 312.500 | 47.851
50| PFE_MAC_2_TX | FXOSC | 2.500 - 125.000 | 0.000 - 0.015
51| PFE_MAC_2_RX | FXOSC | 2.500 - 125.000 | 47.851
Please let me know if the suggestions above solved your problem.
a month ago
574 Views
minersrevolt
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Hey @alejandro_e
Yeah I'm just rebuilding U-Boot for now to change the hwconfig to get past the environment problem using the ``CONFIG_S32CC_HWCONFIG`` option in the defconfig file.
Seeing the following with the clocking... SERDES Ref isn't showing present which looks like a huge red flag here.
Disabling XPCS1_0
Disabling XPCS1_1
s32cc_serdes_phy serdes@40480000: Using mode 2 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: INT Clock selected
s32cc_serdes_phy serdes@40480000: XPCS1 is in reset
s32cc_serdes_phy serdes@40480000: XPCS init failed
pci_s32cc pcie@40400000: Failed to get PHY 'serdes_lane0'
In: serial@401c8000
Out: serial@401c8000
Err: serial@401c8000
Board revision: RDB3
Net:
Found PFE version 0x0101 (S32G3)
PFEng firmware file 'mmc@0:1:s32g_pfe_class.fw' loading failed: -2
No ethernet found.
Hit any key to stop autoboot: 0
=>
=> verifclk
CMU | Monitored | Reference | Expected | Verified
ID | clock | clock | range (MHz) | range (MHz)
-----|--------------|-----------|---------------------|--------------------
0| FXOSC | FIRC | 40.000 | 39.062
1| FIRC | FXOSC | 45.600 - 50.400 | 48.251
2| SIRC | FXOSC | 0.032 | 0.031
Timeout while measuring the frequency of FTM_0_REF
3| FTM_0_REF | FXOSC | 40.000 | 0.000
Timeout while measuring the frequency of FTM_1_REF
4| FTM_1_REF | FXOSC | 40.000 | 0.000
5| XBAR_DIV3 | FIRC | 133.333 | 125.000
6| XBAR_M7_0 | FIRC | 400.000 | 375.000
7| XBAR_DIV3 | FXOSC | 133.333 | 132.812
8| XBAR_M7_1 | FIRC | 400.000 | 375.000
9| XBAR_M7_2 | FIRC | 400.000 | 375.000
24| XBAR_M7_3 | FIRC | 400.000 | 375.000
10| PER | FIRC | 80.000 | 78.125
11| SERDES_REF | FXOSC | 100.000 - 125.000 | 0.000 - 0.015
12| FLEXRAY_PE | FXOSC | 40.000 | 0.000 - 0.015
13| CAN_PE | FXOSC | 80.000 | 47.851
14| GMAC_0_TX | FXOSC | 2.500 - 125.000 | 0.000 - 0.015
15| GMAC_TS | FXOSC | 5.000 - 200.000 | 0.000 - 0.015
16| LIN | FXOSC | 125.000 | 62.500
17| QSPI_1X | FXOSC | 0.000 - 200.000 | 199.218
18| SDHC | FXOSC | 400.000 | 398.437
20| DDR | FIRC | 800.000 | 812.500
21| GMAC_0_RX | FXOSC | 2.500 - 125.000 | 47.851
22| SPI | FXOSC | 100.000 | 47.851
27| A53_CORE | FXOSC | 1300.000 | 1312.500
28| A53_CORE | FIRC | 1300.000 | 1250.000
39| PFE_SYS | FXOSC | 300.000 | 300.781
46| PFE_MAC_0_TX | FXOSC | 2.500 - 312.500 | 0.000 - 0.015
47| PFE_MAC_0_RX | FXOSC | 2.500 - 312.500 | 47.851
48| PFE_MAC_1_TX | FXOSC | 2.500 - 312.500 | 0.000 - 0.015
49| PFE_MAC_1_RX | FXOSC | 2.500 - 312.500 | 47.851
50| PFE_MAC_2_TX | FXOSC | 2.500 - 125.000 | 0.000 - 0.015
51| PFE_MAC_2_RX | FXOSC | 2.500 - 125.000 | 47.851
=> printenv hwconfig
hwconfig=serdes0:mode=pcie&xpcs1,clock=int,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G;serdes1:mode=disable
a month ago
559 Views
minersrevolt
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When I am in PCIE only mode I do see the SERDES clock,
PCIe: BusDevFun VendorId DeviceId Device Class Sub-Class
__________________________________________________________________________
pcie@40400000 RootComplex
| `-- 01:00.00 0x16c3 0x4300 Bridge device 0x04
Net:
Found PFE version 0x0101 (S32G3)
PFEng firmware file 'mmc@0:1:s32g_pfe_class.fw' loading failed: -2
No ethernet found.
Hit any key to stop autoboot: 0
=> printenv hwconfig
hwconfig=serdes0:mode=pcie,clock=int,fmhz=100;pcie0:mode=rc;serdes1:mode=disable
=> verifclk
CMU | Monitored | Reference | Expected | Verified
ID | clock | clock | range (MHz) | range (MHz)
-----|--------------|-----------|---------------------|--------------------
0| FXOSC | FIRC | 40.000 | 39.062
1| FIRC | FXOSC | 45.600 - 50.400 | 48.227
2| SIRC | FXOSC | 0.032 | 0.031
Timeout while measuring the frequency of FTM_0_REF
3| FTM_0_REF | FXOSC | 40.000 | 0.000
Timeout while measuring the frequency of FTM_1_REF
4| FTM_1_REF | FXOSC | 40.000 | 0.000
5| XBAR_DIV3 | FIRC | 133.333 | 125.000
6| XBAR_M7_0 | FIRC | 400.000 | 375.000
7| XBAR_DIV3 | FXOSC | 133.333 | 132.812
8| XBAR_M7_1 | FIRC | 400.000 | 375.000
9| XBAR_M7_2 | FIRC | 400.000 | 375.000
24| XBAR_M7_3 | FIRC | 400.000 | 375.000
10| PER | FIRC | 80.000 | 78.125
11| SERDES_REF | FXOSC | 100.000 - 125.000 | 99.609
12| FLEXRAY_PE | FXOSC | 40.000 | 0.000 - 0.015
13| CAN_PE | FXOSC | 80.000 | 47.851
14| GMAC_0_TX | FXOSC | 2.500 - 125.000 | 0.000 - 0.015
15| GMAC_TS | FXOSC | 5.000 - 200.000 | 0.000 - 0.015
16| LIN | FXOSC | 125.000 | 62.500
17| QSPI_1X | FXOSC | 0.000 - 200.000 | 199.218
18| SDHC | FXOSC | 400.000 | 398.437
20| DDR | FIRC | 800.000 | 812.500
21| GMAC_0_RX | FXOSC | 2.500 - 125.000 | 47.851
22| SPI | FXOSC | 100.000 | 47.851
27| A53_CORE | FXOSC | 1300.000 | 1312.500
28| A53_CORE | FIRC | 1300.000 | 1250.000
39| PFE_SYS | FXOSC | 300.000 | 300.781
46| PFE_MAC_0_TX | FXOSC | 2.500 - 312.500 | 0.000 - 0.015
47| PFE_MAC_0_RX | FXOSC | 2.500 - 312.500 | 47.851
48| PFE_MAC_1_TX | FXOSC | 2.500 - 312.500 | 0.000 - 0.015
49| PFE_MAC_1_RX | FXOSC | 2.500 - 312.500 | 47.851
50| PFE_MAC_2_TX | FXOSC | 2.500 - 125.000 | 0.000 - 0.015
51| PFE_MAC_2_RX | FXOSC | 2.500 - 125.000 | 47.851