I got run m7 core guidance from doc info below,
- Hit any key to stop in the u-boot console
- Disable Data Cache from uboot::
dcache off
- Zero-set SRAM shared memory used by both sample apps::
mw.q 0x34000000 0x0 0x100000
- Load binaries in DDRAM and after is SRAM::
fatload mmc 0:1 0x80000000 IPCF_Example_multi_instance_S32G399_M7_0.bin
cp.q 0x80000000 0x34100000 0x30000
fatload mmc 0:1 0x80000000 IPCF_Example_multi_instance_S32G399_M7_1.bin
cp.q 0x80000000 0x34200000 0x30000
- Start M7 core (the argument is the address of the Interrupt Vector)::
startm7 0x34181000
But I do not know just enabled core running or multi_instance sample binary running, thanks.
Hi,
We understand that you are running the IPCF example provided into the IPCF package for the M7 core.
The steps you have shown are the ones described on the "description.txt" file. Once the "startm7" command is input, feedback will be given by the console saying that the core was successfully initialized.
If you are running the multicore example, M7_0 will start M7_1. A53_0 (or Linux) will only start the M7_0 core.
Please, let us know.
Hi,
What document are you referring to? What IPCF version are you using?
We cannot find anything related to "S32G3_IVT0508_M7_0.bin" under the documents we have access.
Please, let us know.
Hi,
Thanks for your feedback.
If you are running the multicore example (following the "description.txt" steps), no IVT has to be created, since the raw binary is the one being loaded from A53_0 to M7_0 and M7_1.
In summary, no IVT loading is expected from the IPCF multicore example.
Please, let us know.
Hi,
Thanks for your feedback.
The way your application turns on is defined by the application itself. It all comes down on how your application expects to power-on and load the different binaries.
Since you were referring to the IPCF examples, NXP defines the way you are expected to load the binaries into the platform, which is through copying the binary directly from the SD interface into SRAM through u-boot and sending the start command to the M7_0, all through the A53_0 core.
AN13750 defines that the binaries will be fetched from the QSPI interface into SRAM through an NXP provided bootloader and starting each needed core from the M7_0, which was defined as the boot core.
Please, let us know.