Address of memory mapped system counter in S32G2

[carlo-nonato]

Hi,

I'm looking for the address of the memory mapped system counter in the S32G2.

The definition of the system counter is provided by the Armv8 reference manual (DDI 0487H.a, chapter D7 and, in particular, in section D7.1.2). Quoting a bit of it:

The Generic Timer:
  • Provides a system counter that measures the passing of time in real-time.

In section D7.1.1 of the same reference, it is stated that:

The memory-mapped counter module, required
    This module controls the system counter. It has two frames:
        • A control frame, CNTControlBase.
        • A status frame, CNTReadBase.

So basically it must be implemented. Furthermore, it must have a width of at least 56 bits:

The Generic Timer provides a system counter with the following specification:
Width From Armv8.0 to Armv8.5 inclusive, at least 56 bits wide. The value returned by any 64-
           bit read of the counter is zero-extended to 64 bits.
           From Armv8.6, must be 64 bits wide.

Looking at the S32G2 reference manual and its embedded excel files, I can't find such a memory mapped register.

Is it possible that NXP left it undocumented?

Thanks.

[carlo-nonato]

HI @Daniel-Aguirre,

I'm trying to access the CNTPCT_EL0 from outside the A53 cores. In this case I need to read that value from the Cortex-M7.

I have some code that works for the i.MX 8M and for the S32V234 where the register is accessible via two 32-bit memory mapped registers (lower and higher bits). For the i.MX 8M they are documented at page 260, chapter 4.11.4 of its reference manual (rev. 3.1, 06/2021), while for the S32V234 the same goes at page 965, chapter 29.2.19 and 29.2.20 of its reference manual (Rev. 6, 11/2022).

What I want is to be able to do the same for the S32G2.

Thanks.

[Daniel-Aguirre]

Hi,

Thanks for your feedback.

Both i.MX8 and S32V234 share similar architecture, hence the similarities you have mentioned.

S32G is not similar to the previously mentioned families, hence the differences you are pointing out. The register address itself is not mentioned, but the existence is implied [Page 105, S32G2 Reference Manual, Rev. 6, 11/2022].

S32G provides the possibility of using either PIT or STM module as the Generic Timer, which should provide the functionality you are looking for (reading the counts). The following is told under the BSP 33.0 User Manual [Page 92]:

"For this purpose, we use a System Timer Module (STM), 32-bits long. This type of timer has the advantage that its registers can be accessed at SoC level, hence providing global access".

Please, let us know if this information was helpful or not.

[carlo-nonato]

Hi @Daniel-Aguirre,

The register address itself is not mentioned, but the existence is implied

Does this mean that it is undocumented? If so, can you provide us this information?

We would like to leave our codebase as it is, without adding other SoC-dependent code. Obviously the location of this register is SoC-dependent, but we are accessing a "standard" (meaning that as per the Armv8 reference it must be implemented and memory-mapped somewhere) register. Our code is also assuming a 64-bit register.

STM and PIT are different devices and we would prefer not to use them.

Thanks.

[Daniel-Aguirre]

We apologize for the delay.

We have received the following update from the internal team:

"CNTPCT_EL0 is the counter-timer physical count register in ARM-A core, we suggest checking the detailed information about this register in the document of ARM. You could use the instruction as below to access this register. 

"

Please, let us know.

[carlo-nonato]

This is possible only when the instruction is executed from the A53 cores. It doesn't work from the M cores where such register isn't accessible via the MRS instruction. This is why we need a memory mapped register.
Anyway, we are trying to convert our code to use other timer devices (STM or PIT). It isn't perfect and probably it exposes us to other integration problems, but given the limited information contained in the docs, this is the best we can do.
If you can ask for further details it would be nice, but it's not critical for us.

Thanks.

[Daniel-Aguirre]

Hi,

We cannot confirm if the information is undocumented. We will verify with the internal team this specific address.

Please, let us know.

[Daniel-Aguirre]

Hi,

Chapter "5.3.4 Cortex-A53 system counter" provides some information on regards of this topic [Page 102, S32G2 Reference Manual, Rev. 6, 11/2022]:

"The A53 system counter value is driven from a 64-bit counter generated of a divided clock of FXOSC_CLK."

For the information related to ARM itself, it is not integrated into the S32G2/3 Reference Manual, unless it is needed due to a modification or a contradiction over the ARM Reference Manual.

Is there a particular reason you are looking for this information?

Please, let us know.