S32K144W FIRC SPLL input not honored in SDK 4.0.2

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S32K144W FIRC SPLL input not honored in SDK 4.0.2

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marcocade
Contributor I

Hello,

the S32K144W and S32K142W silicon versions allow the SPLL input to be derived from FIRC instead of SOSC.

This configuration is properly selectable in the design studio configuration tool, but generated code does not work as expected, because(in clock_S32K1xx.c file):

SCG_SetSourceSpll() properly selects the SCG.SPLLCFG.SOURCE, but immediately after,  the call to SCG_SetSpllConfiguration() overwrites the SCG.SPLLCFG.SOURCE bit, setting it to zero.

This switches back PLL to SOSC source.

Later, as it is not managed correctly previously, CLOCK_SYS_ConfigureFIRC() is then called and FIRC is switched off (code thinks that FIRC is not used), disabling the main clock source to the sistem.

Please fix this in 4.0.3

@lorenzodaniele 

Thank you

Marco

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marcocade
Contributor I

Dear Robin,

Thank you for you message.

Please update me as  soon as you have some news in terms of timing, and for which release of SDK it will be planned to have this fix included.

Marco

 

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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi Marco,

It will be fixed in next release. For the quick workaround, could you please move the code:

#ifdef SCG_SPLLCFG_SOURCE_MASK
SCG_SetSourceSpll(SCG, spllCfg->src);
#endif
 
From line 2630 to the line: 2607
 
Best Regards,
Robin
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marcocade
Contributor I

Hello,

have you tried that fix?

Because, later, FIRC is stopped as it is not detected to be used, as I wrote in my original post:

"Later, as it is not managed correctly previously, CLOCK_SYS_ConfigureFIRC() is then called and FIRC is switched off (code thinks that FIRC is not used), disabling the main clock source to the system"

 

 

 

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Robin_Shen
NXP TechSupport
NXP TechSupport

During debug, I found that below code will switch FIRC to SOSC:

/* Step 2. Set PLL configuration. */
SCG_SetSpllConfiguration(SCG, spllCfg->prediv, spllCfg->mult);

It was using FIRC before Step 2. Set PLL configuration:

Robin_Shen_0-1631762240039.png

 

It select SOSC after Step 2. Set PLL configuration

Robin_Shen_1-1631762239870.png

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marcocade
Contributor I

Ok, this avoids to overwrite the SOURCE bit of the SCG_SPLLCFG.

But as I said before, LATER in the initialization sequence, at the end of CLOCK_SYS_ConfigureModulesFromScg, a final call to CLOCK_SYS_ConfigureFIRC is done, and due to the fact that it is not understood by the code that FIRC is (indirectly) used as a main clock souce, FIRC is switched off, hanging the CPU:

   /* If clock is used by system, return error. */
    if (SCG_GetFircSystemClockMode(SCG))
    {
        status = STATUS_BUSY;
    }
    /* Disable FIRC */
    else
    {
        /* Clear LK bit field */
        SCG_ClearFircLock(SCG);

        /* Disable monitor, disable clock and clear error. */
        SCG_ClearFircControl(SCG);
    }

I already tried to fiddle with SCG_GetFircSystemClockMode(SCG) in order to avoid it returning false when SPLL is supplied by FIRC, but logic is still not ok, at the end of CLOCK_SYS_ConfigureModulesFromScg it returns BUSY.

I think the logic of that part must be adapted as well.

I hope it is more clear now.

Thank you

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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi marcocade,

Through debugging, I found that the program crash occurred on line 2628.
The CLOCK_SYS_ConfigureSPLL function seems to need to be updated to accommodate the changes introduced by S32K14xW.

Thank you for the report, I'll inform the SDK team about this.

CLOCK_SYS_ConfigureSPLL.png

Best Regards,
Robin
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