XGATE requesting CPU interrupt

[Fast]

However to route to CPU RQST is clear.

Say XGATE sets XGIF ID=$58

With XGIE = 1

and CPU vector set to appropriate ISR, and non-zero priority

Why no interrupt?

Although XGIF Id=58 is normally for CAN0 TX int on XE this cannot prevent XGATE request.

[kef]

Richard,

RQST=0 makes corresponding XGIF_XX_XX flag not used in any way. And when RQST is set, setting XGIF_XX_XX using XGATE SIF instruction triggers corresponding CPU ISR handler. And when it is made triggered, it will run, no matter is corresponding interrupt mask bit set or not. So if you trigger CAN handler, corresponding CAN mask bit is ignored and you should clear not CAN interrupt flag in CAN ISR, but but corresponding CAN XGIF_XX_XX.

See attached prj. It SIF's PIT0 handler. Try setting breakpoints on XGATE and S12 ISR's and also switching RQST in Xgate setup routine.

[Fast]

Sorry

I can not read C code.

XGIF 58 denary = ID $3A

Vector table listing in S12XE says this is for PIT INT E3 

Where as you use PIT INT 0.

What is XGIF_3F_30

And what is CPU doing to PITTF

I think you are triging XGATE with XGSWT1

Then XGATE set XGIF

Why is PIT involved?

[kef]

You didn't mention above that you are using S12XE. My code is for S12XD. Though, it doesn't matter, PIT0 vector is at the same address on both S12XE and S12XD.

• XGIF 58 denary = ID $3A
• Vector table listing in S12XE says this is for PIT INT E3 

Do you mean this XGIF_3F_30_XGIF_3D_MASK? But it is flag mask for XGATE channel $3D, not $3A. Ant it matches low part of CPU12X vector address divided by 2. PIT0 CPU12X vector address is $FF7A. $7A/2 = $3D.

• What is XGIF_3F_30

Well, it is mentioned both in S12XE/S12XD datasheets, also it is defined in both asm and C header files, that come with Codewarrior. By XGIF_XX_XX I meant one of XGIF flags.

I'm sorry you don't understand C. I meant that SIF works only for vectors with RQST=1. SIF doesn't do anything useful in case target channel has RQST=0.

When RQST=1, there can be two scenarios:

1. Hardware interrupt request is handled by XGATE. Then, in case further CPU12X processing is required, XGATE executes SIF with no argument, making the same interrupt channel processed by CPU12X interrupt routine.
2. Same as 1, but you can make other channels than current XGATE thread serviced by CPU12X. To do so you SIF Rx, where Rx contains channel to be triggered for CPU12X processing.

Hope it is more clear.

[Fast]

Possibly

I understood MC9S12XE-Family Reference Manual Rev. 1.24 that:

10.5.2 Outgoing Interrupt Requests

There are three types of interrupt requests which can be triggered by the XGATE module:

4. Channel interrupts

For each XGATE channel there is an associated interrupt flag in the XGATE interrupt flag vector

(XGIF, see Section 10.3.1.8, “XGATE Channel Interrupt Flag Vector (XGIF)”). These flags can be

set through the "SIF" instruction by the RISC core. They are typically used to flag an interrupt to

the S12X_CPU when the XGATE has completed one of its task.

AND

Table 6-8. INT_CFDATA0–7 Field Descriptions

Field Description

7

RQST

XGATE Request Enable—This bit determines if the associated interrupt request is handled by the CPU or by

the XGATE module.

0 Interrupt request is handled by the CPU

1 Interrupt request is handled by the XGATE module

I have RQST = 0 as I want CPU to service it.

[RadekS · Accepted solution]

I think that we found root cause of this issue.

Datasheet says:

Additionally, XGATE interrupts may be raised by the XGATE module by setting one or more of the XGATE channel interrupt flags (by using the SIF instruction). This will result in an CPU interrupt with vector address vector base + (2 * channel ID number), where the channel ID number corresponds to the highest set channel interrupt flag, if the XGIE and channel RQST bits are set.

So, SIF instruction causes CPU interrupt but appropriate Interrupt must be routed to XGATE.

[Fast]

WOW! runs

Thanks everyone

[HSW]

Richard,

Did you maybe clear the INT_XGPRIO register?

[Fast]

No I tested using the XGSWT interrupts directed to CPU, that works fine, but this route is usually to request XGATE actions.

And there a lot more XGIF s, which is more real world.

But fair question HSW

[HSW]

Richard,

Why don't you post your interrupt setup (source code or a memory dump of the XGATE and S12XINT registers) so we can review it.

[Fast]

XGATE code

            LDL      R3,#$38              ;XGIF Interrupt S12 XGSWT1

            SIF        R3

;            LDWD    R3,$0202

;            LDWD    R4,XGSWT

;        STW  R3,(R4,#0)    ;SWT INT  

CPU

        MOVB    #$01,XGIF+8      ;CLEAR FLAG ID $38 (56d)

        MOVW    #$0200,XGSWT      ;CLEAR XGSWT1

        MOVW    TCNT,DEBUG7      ;used to check latency

        INCW    DEBUG8

        RTI

If I set XGSWT1 CPU interrupt runs fine:

DEBUG8 increments

Both XGSWT1 and XGIF ID=$38 cleared

But as shown no XGSWT1 no CPU interrupt no DEBUG8 incrementing.

I assume XGIF ID=$38 is NOT for XGSWT1 but then documentation must be wrong.

Richard

[HSW]

Richard,

you're not showing your S12XINT setup, so I assume that the XGATE software trigger 1 is routed to the XGATE.

In your example, the XGATE code that would set XGSWT1 is commented out. And if it wasn't, you would have a race condition. The XGATE would re-trigger as long as the CPU does not clear the XGSWT1 bit while the XGATE is executing the code in-between the "STW   R3,(R4,#0)" instruction and the next RTS. As soon as the CPU would hit this time window, the software trigger would remain cleared.

[kef]

• I assume XGIF ID=$38 is NOT for XGSWT1 but then documentation must be wrong.

No, it is correct.

Vxst1:              equ   $0000FF70

$70/2 = $38