SPI won't work when SCLK slew rate is limited - 9s12xhz512

[Quimney]

I am running a 9s12xhz512 with a serial chain attached to the SPI. If SRRS bit 6 (SCLK) is set to limit the slew rate of this pin then data always comes back as zero. I can monitor the data at the MISO pin and see the data is clearly both high and low but the read of SPIDR always returns zero. SPISR shows no errors. In case you are wondering if CPOL & CPHA are correct I can tell you that I do see data on the input that is high on both edges of the clock. If I clear bit 6 of the SRRS everything works fine. I am only slowing it down to help pass my EMI problems.

Any Ideas? Thanks in advance.

Added p/n to subject.

Message Edited by NLFSJ on 2009-02-16 07:36 PM

[kef]

Not familiar with S12XHZ, but SRRS bit description says that "1 Enables slew rate control and disables digital input buffer". So I want to ask if you set SRRS bits for both MISO and MOSI, or just for output pin? SRRS descriptions sounds like what you get and if SRRS is set then you can't read this pin. Also SPI also can't read properly from SPI input pin if SRRS=1?

Message Edited by kef on 2009-02-18 04:09 PM

[Quimney]

Good suggestion but the only pin that I am attempting to set slew rate on is the SCLK pin, which is an output. If I don't enable slew rate control on SCLK it works fine, if I do set slew rate control on SCLK it doesn't. Even an MISO pin shorted high will read as zero with SCLK slew rate limited.

[kef]

And did you try to use reduced drive strength register? RDRS also should limit slew rate, but without switching input buffer off.

[bigmac]

Hello,

I am not quite sure what you mean by a "serial chain" connected to the SPI.  Assuming the MCU is the SPI master, I wonder if the problem is because the reduced slew rate clock is problematic for the data timing associated with the SPI slave device(s) that are required to return the data..

  You do not mention the SPI clock rate you are using, but reducing the clock rate might possibly help with any timing issues.

Regards,
Mac

[Quimney]

By serial chain I simply mean 2 chained SPI devices. The MCU is the master and my SPI clock is 500Khz.

The trouble is that when I read the data register I always get zero when I am running the slower edges on SCLK by enabling slew rate control for SCLK. I don't suspect the devices feeding the SPI because I get zero even if I short MISO high. With slew rate control disabled it will read in all ones with the input shorted high. Enabling slew rate control on SCLK will cause it to read in all zeros.

[bigmac]

Hello,

You have tested the MISO pin, but have you viewed the SCLK pin with an oscilloscope, to verify that clock pulses are present?

For the device you are using, for which I am not specifically familiar, I might assume that the slew rate control facility is actually associated with GPIO operation, rather than SPI peripheral operation.  Typically, for Freescale devices, GPIO functionality is over-ridden when a peripheral is enabled, e.g. data direction settings are ignored for the peripheral pins.

I wonder if the enabling of slew rate control at the pin has somehow prevented the clock pulses from being directed to the pin.

There may already be a precedent for this.  I seem to recall specific warnings being given, for HCS08 devices, against the enabling of the high drive current facility for the pins associated with IIC peripheral operation.

Regards,
Mac

[Quimney]

Mac,

I have instrumented SCLK, MOSI, MISO, and my latch clocks and enable lines with a good (500Mhz)scope. Everything looks good and there is no difference in the waveforms between the working settings and the non-working setttings.

You are correct about the slew rate control being a port setting, not a SPI setting. and when you look at the block diagram of the SPI system it doesn't seem like the port would have any effect on the SPI logic but.... It sure seems to.

[bigmac]

Hello,

Out of curiosity, is the underlying GPIO pin corresponding to MISO configured for input or output, and do you have slew rate control also enabled for this pin?  I am thinking that it might be somehow possible for the GPIO to force the MISO input to the SCI module low, whenever there is slew rate control.  But I can't see why the SCLK pin should affect MISO.

Obviously, the solution is simple - don't use the slew rate control facility.  Are the waveform edges for the SCLK signal actually slowed, when enabled?

Regards,
Mac

A further thought.  To achieve reduced slew rate of the SCLK signal, to control EMI, you might try simply placing a resistor in series with the SCLK line, in close proximity to the MCU (master).  With a SPI clock as low as 500kHz, the resistor value could probably be as much as 4.7k, or even 10k.  This will form a low pass filter in conjunction with the input capacitance of the slave SPI devices.



Message Edited by bigmac on 2009-02-17 09:14 PM

[Quimney]

I have tried all approriate pins slew rate controlled, and only SCLK slew rate controlled.

I have set the data direction for all lines according to their purpose.

I have spent way too much time on this issue and it's too late to change the hardware.

What I can say is that I think I will pass EMC now that I have reduced the drive on the port pins. I don't need the full drive and the edges are much improved. Reducing the drive seems to have no ill effects on the SPI module so it's time to move on for now.

I sure would like to understand what happened but.... time is a cruel taskmaster and I've got miles to go before I sleep.

Thanks for your help.

Darrell

[Shur]

Did any of you actually read Quimney's posts?  Everything you've suggested he already explained in his original post with the exception of the reduced drive which he addressed later.

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Quimney wrote:

What I can say is that I think I will pass EMC now that I have reduced the drive on the port pins. I don't need the full drive and the edges are much improved. Reducing the drive seems to have no ill effects on the SPI module so it's time to move on for now.

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I'm sorry I can't be of any help Quimney.  Hopefully Freescale is aware of your issue and will be able to provide an intelligent response.  Best of luck.

Shur

[kef]

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Shur wrote:

Did any of you actually read Quimney's posts?  Everything you've suggested he already explained in his original post with the exception of the reduced drive which he addressed later.

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Taken.

I wonder what is the principal difference between enabled slew rate control and enabled reduced drive. Is enabled slew rate control producing nicier edges? S12XHZ docs seem being silent about this.

[Quimney]

Slew rate limits the rise and fall time of the signal with the full drive capability and the spec defines what the rate will be so it should be predicatable...

Reducing the drive can have a similar effect on the rise/fall times but only because less energy is going into changing the signal. The actual shape of the resulting waveform is going to be very dependant on what loads you have on the line. With a very light load the risetime doesn't change much, as the load increases it has more trouble changing state and the risetime is affected more severely.

Reducing the drive seems to do a better job of reducing the overshoot due to the decrease in energy. changing slew rate will change the slope/risetime but the overshoot is often still present.

Bottom line: slew rate will slow the rise time according to the datasheet. Reducing the drive can have a similar same effect but it will be circuit dependant.

[kef]

Thanks for your explanation. I didn't think full drive and slew rate control is possible in these micros. Also pdf search for "slew rate" failed and I thought there no related word in Electrical Characteristics. It looks like there are 4 possible slew/drive_strength modes, since datasheet specifies defferent slew rates for slew enabled with partial drive and slew enabled with full drive. Good to know.