SPI + 2 Timers Implementation S12ZVL128

[heshamyassin]

Hello,

I'm using MC9S12ZVL128 and I want to implement 2 timers. One for OS (Periodic Timer) and one for SPI (One Shot Timer). I configured the timers on TIM0 Channel 0 and TIM1 Channel 0.

I'm using SPI as master for sending command to another micro-controller and the problem is that when the SPI interrupt fires, it stops OS timer and SPI timer stops as well. However when SPI is not initialized, the two timers work well.

Please find below the code for SPI configuration and SPI interrupt.

void Spiinit ( void)
{

/*!Pseudo: Set SPI Clock Phase */
SPI0CR1_CPHA = 0;

/*!Pseudo: Set SPI Clock Polarity */
SPI0CR1_CPOL = 0;

/*!Pseudo: Set SPI Data Transfer Width */
SPI0CR2_XFRW = 0;

/*!Pseudo: Set SPI Baud Rate */
SPI0BR = 0x0F;

/*!Pseudo: Set SPI Mode Fault Enable */

SPI0CR2_MODFEN = 1;

/*!Pseudo: Set SPI Slave Select */
SPI0CR1_SSOE = 1;

/*!Pseudo: Set Data transmitted MSB/LSB first */
SPI0CR1_LSBFE = 1;

/*!Pseudo: Select SPI Master/Slave Mode */
SPI0CR1_MSTR = 1;

/*!Pseudo: Set Bidirectional Pin Configurations */
SPI0CR2_BIDIROE = 0;

SPI0CR2_SPC0 = 0;

/*!Pseudo: Set SPI Interrupt */
SPI0CR1_SPIE = 1;
/*!Pseudo: Enable SPI */
SPI0CR1_SPE = 1;

}

interrupt VectorNumber_Vspi0 void SPIInterrupt(void)
{
if(SPI0SR_SPIF==1)
{
u8ReadData= SPI0DR;
}

}

the interrupts priorities as follows:

/* IT Timer0 ch0 */
INT_CFADDR =0x73;
INT_CFDATA0 = 0x06;

/* IT Timer1 ch0 for SPI interface */
INT_CFADDR = 0x2B;
INT_CFDATA0 = 0x06;
/* IT SPI interrupt (connected to SPI0) priority */
INT_CFADDR = 0x68;
INT_CFDATA7 = 0x01;

I have also another question, I don't understand the difference between two interrupts (SPIE, SPTIE), and how to clear them?

[danielmartynek]

Hi Hesham,

You say it stops both timers, you mean their interrupts are not being executed, right?

The SPIE bit enables SPI interrupt if SPIF flag is set (received data has been transferred into the SPI data register) or Mode Fault Flag is set provided MODFEN bit is set. I see the MODFEN is set.

So please check MODF flag. It must be cleared in the ISR.

The SPTIE bit enables SPI interrupt if SPTEF flag is set indicating that the transmit data register is empty.

As you can see in Tables 19-9,10 in order to clear SPIF and SPTEF flags, you must read the flags and then read or write to the data register. In order to clear MODF, read the flag and write to SPICR1 register.

The code may look like this

if(SPI0SR & (SPI0SR_SPIF_MASK | SPI0SR_MODF_MASK)){
   if (SPI0SR & SPI0SR_MODF_MASK) {
       SPI0CR1_MSTR = 1;
   }
   else {
       data = SPI0DRL;
   }
}‍‍‍‍‍‍‍‍

Regards,

Daniel

[heshamyassin]

Hello Daniel,

Thanks for your support.