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Posted: Thu Dec 29, 2005 10:16am
Hi,
I'm using the 68hcs12c64 processor and having the following problem with its SCI module:
Whenever I receive a Uart signal (checked on a scope) at the SCI interface, the SCI interrupt is asserted. But the Transmit interrupt flag is asserted instead of the Receive interrupt flag, with the transmit interrupt disabled.
Does anyone have an idea of what may be happening.
Thanks and regards,
Posted: Thu Dec 29, 2005 10:49am
> I'm using the 68hcs12c64 processor and having the
> following problem with its SCI module:
>
> Whenever I receive a Uart signal (checked on a scope)
> at the SCI interface, the SCI interrupt is asserted.
> But the Transmit interrupt flag is asserted instead of
> the Receive interrupt flag, with the transmit
> interrupt disabled.
>
> Does anyone have an idea of what may be happening.
Yes. With the little information you gave, I can say that something is probably wrong with your source code.
Specifically I can say that the tx interrupt should be asserted as you say it is, unless it is currently sending a character also. Anyway, that's why you sould not enable tx irq until you have data to send.
Posted: Thu Dec 29, 2005 11:53am
> Whenever I receive a Uart signal (checked on a scope)
> at the SCI interface, the SCI interrupt is asserted.
> But the Transmit interrupt flag is asserted instead of
> the Receive interrupt flag, with the transmit
> interrupt disabled.
I am not sure about the receive interrupt, but the transmit interrupt flag is set because the transmitter is empty. This flag indicates the status of the transmitter, whether the transmit interript is enabled or not.
Regards,
Posted: Thu Dec 29, 2005 1:53pm
Yes, I forgot this detail, otherwise we would not be able to perform polling over Tx flag. Fortunately I found out the problem: another issue of Code Warrior's PE: it looses information of the status flag after reading it.
Thanks
