S12ZVL aclk TRIM

[charudattaingal]

Dear All,

i want to trim the aclk clock value Requesting assistance for that

CPMUPROT = 0x26U;

CPMUCLKS_COPOSCSEL1 = 0x1U;

CPMUCLKS_CSAD = 0x1U;

CPMUPROT = 0x00U;

CPMUACLKTR = 0x00;

CPMUCOP = 0x41U;

in above code i trim the ACLK to mid as ACLK is default value is 20k CPMUACLKTR = 0x00; will trim ACLK to half i.e 10k

so watchdog input aclk clock value is 5 k

CPMUCOP = 0x41U; with this i get 25ms watchdog time period

not getting expected output

[RadekS]

Hi Charudatta,

In attachment you could find simple example code how to trim ACLK at S12ZVL MCU.

If, you would like trim ACLK clock to different clock than 20kHz, please modify INTERVAL_10MS value inside code.

Unfortunately I am afraid that ACLK trimming isn’t enough flexible for that task (ACLK at 10kHz).

I was able set ACLK at my board in range from 16kHz to 26kHz. Therefore I suppose that watchdog period 25ms with ACLK as source clock will be not achievable.

You could achieve watchdog period with ACLK clock source only around 16ms (CPMUCOP = 0x41U; ACLK=16kHz) or around 40ms (CPMUCOP = 0x42U, ACLK=26KHz);

I would like to note that range approximately 16kHz to 26kHz are just measured values on my board. It is possible that this range also could slightly vary between MCUs (therefore we have trimming option).

I hope it helps you.

Have a great day,
RadekS

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