This example shows a few possible configurations of the S12PWM8B8CV2 PWM module.
Five PWM channels are configured with different clock source, polarity, alignment, period and duty-cycle.
Four clock sources (A, B, SA, SB) are derived from bus clock using dividers.
Selected polarity of PWM channel determines the duty-cycle whereas the alignment determines the period of the PWM signal.
Four 8-bit channels (4-5, 6-7) are concatenated into two 16-bit channels.
Channels 4 and 6 become high-order channels while channels 5 and 7 become low-order channels.
These low-order channels (5 and 7) are the output channels routed to a port
and they configure the clock, polarity, alignment and enablement of the PWM signal.
Period and duty-cycle of the signal are configured with both the low-order and high-order channels.
The period registers (PWMPERx) and the duty-cycle registers (PWMDTYx) are double buffered.
When they are rewritten while the channel is enabled, the change will not take effect until one of the following occurs:
1. The effective period ends
2. Counter resets
3. The channel is disabled
