HCS12 problem with address latching during write cycle

[bernacek]

Hello All,

I'm using MC9S12DT256 microcontroller device configured with access to external RAM memory. And I have a big problem with address latching from multiplexed address-data bus during write cycle. I'm using 74AC573 latch with standard configuration to latch address by negative edge of ECLK signal (there is inverter AC04 beetween ECLK uC pin and AC573 latch in order to negate ECLK signal). During read cycle from external memory this works fine but while making a write cycle the latch AC573 doesn't catch the address and latches the data. It seems that address vanishes to fast compared to ECLK edge and inverter makes additional delay - all these things cause that AC573 can't latch valid address. How can I fix this?

Does anybody have similar problems? I need an urgent help with this case!!! What can I do to fix this problem! Please HELP me!!!

[Steve]

There are two applications notes that may help in your case:

AN2287 describes the interface and how it works and AN2408 gives several schematic examples with logic analyzer traces. Have a look to see if they help.

[bernacek]

OK.

I    **** out a great solution!!

I have ORed ECLK (4Mhz) and a clock (8Mhz) and with 3 NOR gates its working!

68HCS12 is a piece of   **** !!!   

 I can't believe, that's Freescale's design!!!

Message Edited by bernacek on 2006-06-25 12:49 PM

(Alban sanitised unappropriate language)

Message Edited by Alban on 2006-06-26 02:39 PM

[imajeff]

bernacek,

I can't picture what you're trying to say... maybe wait 'till your drugs wear off and explain it again?

See, usually if you have a habit of inserting words that have no context in a sentence, it loses meaning...

If I could see the arrangements of the gates I might see what you mean.

[imajeff]

Oh, I found something more. I had forgot where to look, but you can stretch ECLK in the MISC register. So that's basically what I've done with my old design. Of course it would slow down code accessing the external memory. See S12MMCV4.pdf for MISC register.

[imajeff]

What's the timing comming from the MCU? It has been said that S12 is dificult to handle timing. I'm thinking a slower bus speed might prove if it is a timing problem.

People have said that S12X is the solution for the problem. Much of this was discussed in the 68HC12 yahoogroup before Freescale forums opened.

[bernacek]

Bus clock is 4MHz so it is relatively small value. Unfortunatelly, I can't change processor in my project. I need add some software and/or create some signal that can latch address when it is valid. Does anyone have any clue?

[imajeff]

I was worried that slowing the bus cycle would not solve it. I guess the timing dificulty is not just related to that. You could probably change your logic gates to respond faster, but of course not cheap nor easy (maybe by using a PLD).

Try looking at:

http://groups.yahoo.com/group/68HC12/message/9931?threaded=1&var=1
S12MEBIV3.pdf

I think there are some good hints. I think I was just in a good discussion in this Freescale forum which referenced more documents, but can't find it at the moment. It seemed like in the last month.

In my XC68HC912BC32, I configure ESTR to stretch the external ECLK in a certain address range. I don't see that much control in this one.