TLB Overlap in T2080RDB_SPIFLASH_config V2.0-1703

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TLB Overlap in T2080RDB_SPIFLASH_config V2.0-1703

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albertandreasjr
Contributor II

I have built the T2080RDB_SPIFLASH_config of version V2.0-1703 and put it in SPI flash (of course with the other images, fman, Cortina, and U-Boot Environment). When I do a reginfo I see an overlap of the TLBs; yet the build seems to run fine in u-boot.

My understanding is that overlapping TLBs are an error based upon this document e6500 Core Reference Manual Supports e6500 E6500RM Rev 0 06/2014.

Are overlapped TLBs an error?

I was wondering why I get no error interrupt described in Paragraph 6.2.5.1 (Possibly U-Boot has them turned off)?

Is it working errant-ly in an "Undefined State"?

I was hoping that overlaps are allowed in a T2080. I need to remap the TLBs before running vxWorks and I want to do the remapping in vxWorks.

Right now I am avoiding any overlaps by ensuring that U-Boot use a TLB in a specific range.

Is there reference code for remapping specific TLBs to DDR and CCSR. This would need to work no matter what TLBs are assigned on entry? 

(U-Boot dynamically assigns the DDR to the first free TLB)


=> reginfo
TLBCAM entries
entry 00: V: 1 EPN 0xfffff000 RPN 0x7ffff000 size:4 KiB
entry 01: V: 1 EPN 0xfe000000 RPN 0xffe000000 size:16 MiB
entry 02: V: 1 EPN 0xe0000000 RPN 0xfe0000000 size:256 MiB
entry 03: V: 1 EPN 0x80000000 RPN 0xc00000000 size:512 MiB
entry 04: V: 1 EPN 0xa0000000 RPN 0xc20000000 size:256 MiB
entry 05: V: 1 EPN 0xb0000000 RPN 0xc30000000 size:256 MiB
entry 06: V: 1 EPN 0xc0000000 RPN 0xc40000000 size:256 MiB
entry 07: V: 1 EPN 0xf8000000 RPN 0xff8000000 size:256 KiB
entry 08: V: 1 EPN 0x00000000 RPN 0x00000000 size:2 GiB
entry 09: V: 1 EPN 0xf4000000 RPN 0xff4000000 size:16 MiB
entry 10: V: 1 EPN 0xf5000000 RPN 0xff5000000 size:16 MiB
entry 11: V: 1 EPN 0xf6000000 RPN 0xff6000000 size:16 MiB
entry 12: V: 1 EPN 0xf7000000 RPN 0xff7000000 size:16 MiB
entry 13: V: 1 EPN 0xf0000000 RPN 0xf00000000 size:32 MiB
entry 14: V: 0 EPN 0x00000000 RPN 0x00000000 size:4 KiB
entry 15: V: 0 EPN 0x00000000 RPN 0x00000000 size:4 KiB
entry 16: V: 1 EPN 0xff800000 RPN 0xfff800000 size:64 KiB
entry 17: V: 1 EPN 0xffdf0000 RPN 0xfffdf0000 size:4 KiB
entry 18: V: 0 EPN 0x00200000 RPN 0x00200000 size:4 KiB
entry 19: V: 1 EPN 0x00000000 RPN 0x00000000 size:2 GiB

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albertandreasjr
Contributor II

Thank you very much!

The reason I am not getting a fault is because bit EN_L2MMU _MHD appears to be off.

This bit enables multiple hit detection.  Since this was off I did not get the multiple hit detection error.  Paragraph 2.7.5 of E6500RM describes the bit.  And according to the paragraph just above the referenced figure (6.2.5.1), when the bit is undefined the translation is undefined.

So it appears that the described system is running with translations "Undefined"; albeit dangerously without fault.  I will keep the code in my release that prevents this condition.

Al

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yipingwang
NXP TechSupport
NXP TechSupport

Hello A EAJr,

A hit to multiple matching TLB entries is considered a programming error. If this occurs, the TLB generates an invalid address, TLB entries may be corrupted, and a machine check or error report interrupt is generated if HID0[EN_L2MMU_MHD]. If HID0[EN_L2MMU_MHD] is not set when the error occurs, the resulting translation is undefined.

Please refer to "Figure 6-4. Virtual address and TLB-entry compare process" in https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf?fsrch=1&sr=1&pageNum=1 .

Translation ID(TID) field of TLB entry compared with PID. PID defined by PID register, is associated with each effective address generated by the processor, used to construct virtual addresses for accessing memory.


Have a great day,
TIC

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