SDn_REFCLK rise/fall edge rates for LS1046ARDB don't meet spec?

[matthej]

So the LS1046ARDB eval board uses the 6V49205 clock driver for SDn_REFCLK1 clock output going to the LS1046 processor.
The 6V49205 specs the slew rate as:

But the LS1046A  processor specifies it as:

So it looks like the clock buffer has a faster (5.7 vs 4) slew rate compared to what the LS1046 expects to see at its input.

Am I missing something?

Thanks!

[ufedor · Accepted solution]

Results of simulating 6V49205 (IBIS model Fast-Strong) in HyperLynx:

1) PCIET/C_LR1 unconnected

Slew Rate at the 6V49205 die is 4.0 V/ns

2) PCIET/C_LR1 connected as in the LS1046ARDB schematics

Slew Rate at the LS1046A die is 2.2 V/ns