LS1046A DDR4 training failed

[JasonLi-10]

I have a LS1046 board, using a dual rank DIMM with two chip select, and reported DDR training failed when starting. The detailed log is as follows:

INFO: SoC workaround for Errata A008850 Early-Phase was applied
INFO: SoC workaround for Errata A010539 was applied
INFO: RCW BOOT SRC is QSPI
INFO: SoC workaround for DDR Errata A008511 was applied
INFO: SoC workaround for DDR Errata A009803 was applied
INFO: SoC workaround for DDR Errata A009942 was applied
INFO: SoC workaround for DDR Errata A010165 was applied
INFO: platform clock 700000000
INFO: DDR PLL1 2100000000
INFO: DDR PLL2 500000000
INFO: time base 8 ms
INFO: Parse DIMM SPD(s)
INFO: Controller 0
INFO: DIMM 0
INFO: addr 0x51
INFO: checksum 0xe404fd5b
INFO: n_ranks 2
INFO: rank_density 0x200000000
INFO: capacity 0x400000000
INFO: die density 0x5
INFO: primary_sdram_width 64
INFO: ec_sdram_width 0
INFO: device_width 8
INFO: package_3ds 0
INFO: rdimm 0
INFO: mirrored_dimm 1
INFO: rc 0x1f
INFO: n_row_addr 16
INFO: n_col_addr 10
INFO: bank_addr_bits 0
INFO: bank_group_bits 2
INFO: edc_config 0
INFO: burst_lengths_bitmask 0xc
INFO: tckmin_x_ps 750
INFO: tckmax_ps 1600
INFO: caslat_x 0x1ffc00
INFO: taa_ps 13750
INFO: trcd_ps 13750
INFO: trp_ps 13750
INFO: tras_ps 32000
INFO: trc_ps 45750
INFO: trfc1_ps 350000
INFO: trfc2_ps 260000
INFO: trfc4_ps 160000
INFO: tfaw_ps 21000
INFO: trrds_ps 3000
INFO: trrdl_ps 4900
INFO: tccdl_ps 5000
INFO: trfc_slr_ps 0
INFO: twr_ps 15000
INFO: refresh_rate_ps 7800000
INFO: dq_mapping 0x16
INFO: dq_mapping 0x36
INFO: dq_mapping 0x16
INFO: dq_mapping 0x36
INFO: dq_mapping 0x16
INFO: dq_mapping 0x36
INFO: dq_mapping 0x16
INFO: dq_mapping 0x36
INFO: dq_mapping 0x0
INFO: dq_mapping 0x0
INFO: dq_mapping 0x2b
INFO: dq_mapping 0xc
INFO: dq_mapping 0x2b
INFO: dq_mapping 0xc
INFO: dq_mapping 0x2b
INFO: dq_mapping 0xc
INFO: dq_mapping 0x2b
INFO: dq_mapping 0xc
INFO: dq_mapping_ors 1
INFO: done with controller 0
INFO: cal cs
INFO: cs_in_use = 3
INFO: cs_on_dimm[0] = 3
NOTICE: UDIMM
INFO: Time after parsing SPD 548 ms
INFO: Synthesize configurations
INFO: cs 0
INFO: odt_rd_cfg 0x0
INFO: odt_wr_cfg 0x4
INFO: odt_rtt_norm 0x3
INFO: odt_rtt_wr 0x0
INFO: auto_precharge 0
INFO: cs 1
INFO: odt_rd_cfg 0x0
INFO: odt_wr_cfg 0x0
INFO: odt_rtt_norm 0x0
INFO: odt_rtt_wr 0x0
INFO: auto_precharge 0
INFO: cs 2
INFO: odt_rd_cfg 0x0
INFO: odt_wr_cfg 0x0
INFO: odt_rtt_norm 0x0
INFO: odt_rtt_wr 0x0
INFO: auto_precharge 0
INFO: cs 3
INFO: odt_rd_cfg 0x0
INFO: odt_wr_cfg 0x0
INFO: odt_rtt_norm 0x0
INFO: odt_rtt_wr 0x0
INFO: auto_precharge 0
INFO: ctlr_init_ecc 0
INFO: x4_en 0
INFO: ap_en 0
INFO: ctlr_intlv 0
INFO: ctlr_intlv_mode 0
INFO: ba_intlv 0x40
INFO: data_bus_used 0
INFO: otf_burst_chop_en 1
INFO: burst_length 0x6
INFO: dbw_cap_shift 0
INFO: Assign binding addresses
INFO: ctlr_intlv 0
INFO: rank density 0x200000000
INFO: CS 0
INFO: base_addr 0x0
INFO: size 0x400000000
INFO: CS 1
INFO: base_addr 0x0
INFO: size 0x400000000
INFO: base 0x0
INFO: Total mem by assignment is 0x400000000
INFO: Calculate controller registers
INFO: Skip CL mask for this speed 0x4000
INFO: Skip caslat 0x4000
INFO: cs_in_use = 0x3
INFO: cs0
INFO: _config = 0x80040422
INFO: cs[0].bnds = 0x3ff
INFO: cs_in_use = 0x3
INFO: cs1
INFO: _config = 0x80000422
INFO: cs[1].bnds = 0x3ff
INFO: sdram_cfg[0] = 0xc5004000
INFO: sdram_cfg[1] = 0x401141
INFO: sdram_cfg[2] = 0x0
INFO: timing_cfg[0] = 0xd1770018
INFO: timing_cfg[1] = 0xf2fc8245
INFO: timing_cfg[2] = 0x594197
INFO: timing_cfg[3] = 0x2161100
INFO: timing_cfg[4] = 0x220002
INFO: timing_cfg[5] = 0x5401400
INFO: timing_cfg[6] = 0x0
INFO: timing_cfg[7] = 0x26600000
INFO: timing_cfg[8] = 0x5446a00
INFO: timing_cfg[9] = 0x0
INFO: dq_map[0] = 0x5b65b658
INFO: dq_map[1] = 0xd96dab30
INFO: dq_map[2] = 0xaccaccac
INFO: dq_map[3] = 0x30000001
INFO: sdram_mode[0] = 0x3010631
INFO: sdram_mode[1] = 0x100000
INFO: sdram_mode[9] = 0x8400000
INFO: sdram_mode[8] = 0x500
INFO: sdram_mode[2] = 0x10631
INFO: sdram_mode[3] = 0x100000
INFO: sdram_mode[10] = 0x400
INFO: sdram_mode[11] = 0x8400000
INFO: sdram_mode[4] = 0x10631
INFO: sdram_mode[5] = 0x100000
INFO: sdram_mode[12] = 0x400
INFO: sdram_mode[13] = 0x8400000
INFO: sdram_mode[6] = 0x10631
INFO: sdram_mode[7] = 0x100000
INFO: sdram_mode[14] = 0x400
INFO: sdram_mode[15] = 0x8400000
INFO: interval = 0x1ffe0000
INFO: zq_cntl = 0x8a090705
INFO: ddr_sr_cntr = 0x0
INFO: clk_cntl = 0x2000000
INFO: cdr[0] = 0x80040000
INFO: cdr[1] = 0xc1
INFO: wrlvl_cntl[0] = 0x86750609
INFO: wrlvl_cntl[1] = 0xa0b0c0d
INFO: wrlvl_cntl[2] = 0xf10110e
INFO: debug[28] = 0x61
INFO: Time before programming controller 814 ms
INFO: Program controller registers
INFO: Reading debug[9] as 0x32003400
INFO: Reading debug[10] as 0x36003900
INFO: Reading debug[11] as 0x3e004000
INFO: Reading debug[12] as 0x42004400
INFO: cpo_min 0x32
INFO: cpo_max 0x44
INFO: debug[28] 0x6a0061
INFO: Optimal cpo_sample 0x62
ERROR: Found training error(s): 0x1002
ERROR: Writing DDR register(s) failed
ERROR: Programing DDRC error
ERROR: DDR init failed.
INFO: SoC workaround for Errata A008850 Post-Phase was applied
INFO: RCW BOOT SRC is QSPI
NOTICE: Incorrect DRAM0 size is defined in platform_def.h
ERROR: mmap_add_region_check() failed. error -22
ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:790
BACKTRACE: START: assert
0: EL3: 0x1000720c
1: EL3: 0x10008e44
2: EL3: 0x100088e8
3: EL3: 0x1000802c
4: EL3: 0x10007b90
5: EL3: 0x10006940
6: EL3: 0x100000e0
BACKTRACE: END: assert

May I ask what does "ERROR: Found Training ERROR (s): 0x1002" mean and how should I solve it? Thank you.