LS1046A Custom Design HRESET_B not released

[bryceferguson]

Hello,

I am working to bringup a custom design making use of the LS1046A processor. (Board design used the RDB as a reference).  I have verified that all power rail voltages are correct and have have measured the power sequencing timing which all appear to be withing the tolerances found in the datasheet. The issue I am experiencing is that I am not able to bring the processor out of reset. When measuring, I found that the processor is not releasing the HRESET_B signal. The reference manual indicates that the processor will hold this line low while it is performing initialization and will release it after loading the RCW and locking PLL's, etc. Thinking perhaps I had an error in my RCW, I used the built-in RCW values instead. (I strapped the processor with both the 0x9E and 0x9F RCW values with the same result).

At this point, I'm at a bit of a loss. My clocks are provided on time, my slew rates are all within spec, and I am holding the strapping values for the correct amount of time before releasing them. The reference manual also indicates that the PBL will toggle the RESET_REQ signal if it has encountered an error, but I am not seeing this happen. So my conclusion currently is that the PBL is not even being executed which, to me, is a sign that the processor is still in a reset state.

Is there something here that I am missing? Anywhere I should look next? My timings are within spec, but do not match the RDB exactly (I probed the relevant signals on the board). How sensitive is the power sequencing on the LS1046?

Thanks in advance.

[ufedor]

As first checking stage please inspect:

1) POR levels of all signals explicitly mentioned in the notes to the QorIQ LS1046A, LS1026A Data Sheet, Table 1. Pinout list by bus.

2) HRESET_B is not asserted externally

3) SerDes reference clocks conform to the Data Sheet requirements.

If the issue will not be resolved, it is more convenient to perform next bring-up stage as Technical Case:

https://community.nxp.com/thread/381898 

[bryceferguson]

Hello,

Thanks for your response.  I have verified that all of the above are in a good state. One question I did have about your last point, however: Is this required in order for the power-on reset sequence to complete? As I stated earlier, we are not able to observe the RESET_REQ signal, so I believe we are unable to execute the PBL. Are SerDes reference clocks required in order execute the PBL, or are they required later on while PBL is already setting up the system?

Thanks

[ufedor]

Please use a digital scope to check whether RCW is read from an external flash.

[bryceferguson]

We have strapped the hardware to use the hard-coded RCW, not the RCW from flash.

[ufedor]

Please create a Technical Case so I will be able to check the processor connection schematics.

[bryceferguson]

Thank you for your above answers.

To tie off the thread, I have solved the issue with the power sequencing in my CPLD code. Because the original code I had was causing this issue, I re-wrote it and I no longer see the issue.