IFC Bus corrupts NvSRAM during power-down

[nsutch]

Hi,

We have a custom PCB using a T1040 processor with an NvSRAM attached to the IFC bus, running in GPCM mode. We notice that once a power-down sequence is initiated by our power manager, in response to the boards input supplies going off, there is a sequence of transactions on many of the IFC signals. This includes WE and CS signals which unintentionally enables writes to the NvSRAM with whatever is on the IFC bus at the time. When we turn the card back on, certain locations in the NvSRAM are corrupted. This seems to occur whether the T1040 is in reset or not during power-down.

We don't suspect crosstalk as a number of IFC signals exhibit the same pattern, including an unused CLE signal which has a very short trace to a pull-up. The fact that CLE transitions in the same way points the finger towards the T1040 rather than the NvSRAM as only the T1040 connects to this net.

I have attached a scope trance which shows the NvSRAM chip select CS2 (yellow) and CLE (blue) with the transactions occurring just before the +1V8 supply to the IFC bus turns off (Where the signals start to roll off).

We have managed to 'solve' the issue by changing our power-down sequence so that the +1V8 supply to the IFC turns off first before the T1040 core and +3V3 supply but it seems like a strange behaviour.

Has anyone seen anything similar? Any thoughts on what might be causing these transactions?

Thanks,

Nick

[Bulat · Accepted solution]

I believe the bouncing on CS2 and CLE signals happens after VDD/VDDC supplies are on ramp down way. If so, it is not strange behavior, it is rather expected. Note that IFC core works under VDD/VDDC (1V) power rail, its signals go to external bus (1.8V) through voltage translators. As soon as you are removing VDD/VDDC power, there is a time (some specific VDD level) when internal logic stops properly working and I/O signals can output some glitches, like you observed.
I would note that normally NVSRAM-like devices require at least one additional external logic gate on CS signal that provides high level of the signal during power-up and power-down times, regardless of the processor's output behavior. We can not guarantee correct behavior of  I/O signals when supply voltage levels are out of their nominal values.

Regards,

Bulat

[nsutch]

Hi Bulat,

Thank you for your clarification. This would explain why turning off the I/O supplies first before VDD/VDDC has fixed the issue.

This would be useful information to include in Section 3.3 (Power-Down Requirements) of the datasheet.

Thanks,

Nick