DDR Validation - endianness error

[sp_qoriq]

I'm trying to use the DDR validation suite in QCVS to get optimal values for WRLVL registers for our custom board. We have the u-boot loading, but it fails to detect the DIMM capacity of channel 1 of 1st and 2nd memory controllers. I'm able to connect to the target and import the settings from the target as well. But the validation fails with "error: endianness". I have tried starting with Auto configuration and Import from Target configuration. udimm part is Mircon, MTA9ASF1G72AZ.

Sometimes I can get past the endianness error; but validation fails before the final step with some "internal error".

Reading from SPD also fails in the DDRv tool. Please see attached pictures. I have also attached the u-boot log for reference.

Can someone help me with these errors, please?

Thanks. 

[sp_qoriq]

We figured out the issue with our JTAG circuit. Thanks for the help addiyi‌

[sdhunna]

We are seeing similar errors for our custom board bring-up.  Can I ask what you changed in your JTAG that got this working for you?

[pb3]

I know that's it's kinda old topic - but have you managed to solve it? Was it a JTAG issue? If so, how did you manage to solve it?

[sp_qoriq]

Thanks for the reply, addiyi‌. That is exactly the error I'm seeing along with - "Subcore error encountered during multicore operation". Please see below:

(bin) 19 % ccs::reset_to_debug
Received CMD_RESET_TO_DEBUG
Sending CMD_SERVER_ALIVE
Sending CMD_SERVER_ALIVE
Sending CMD_SERVER_ALIVE
nhti command done - Subcore error encountered during multicore operation
Received CMD_PARSE_ERROR
nhti command done - Ok
LS2085A: Core not responding

Also, I can see that the SoC is going through the reset when DDRv starts reading from SPD. Is CCS unhappy because reset is not complete within certain seconds? Based on what I see on the CPU/CCS console, "Subcore error ...." message is printed out around the same time as the "Programming Controller %d" step of DDR initialization...   

But, our jtag seems to be working fine. We have used it extensively (breakpoints/examine memory, etc.) to debug the u-boot bringup. Anything in particular we should pay attention to?

[addiyi · Accepted solution]

The issue is related with resetting the board over jtag. It could be because of incorrect RCW or because of some issue on jtag implementation. DDRv will reset the SoC before starting Read SPD action and will failed if it cannot do that.

A simple way to check this is to directly use ccs with the following commands:

delete all

config cc cwtap:<ip_addr>

ccs::config_chain {ls2085a dap}

display ccs::get_config_chain

ccs::reset_to_debug

If the message returned by the last command is Core not responding you should double check the jtag on your board.

Adrian

[sp_qoriq]

As you can see from the pictures/logs, the SoC used is LS2088A, rev 1.1. Appreciate the help...

[sp_qoriq]

QCVS version is: 4.10.0.0001-20170917. Running on Windows-10.

[addiyi]

Also provide the SoC used.

Adrian

[addiyi]

What is your QCVS version and your running OS?

Adrian