C290PCIe-RDB Rev C board timing constraints .sdc file request

[mikedubya]

I was looking to add some addressable registers to the CPLD on my C290PCIe-RDB Rev C board.  I have already used the Altera Programming Tool to verify the contents of the CPLD on the board against the oamp-v2.2.pof design file.

But to build my own image, I would need the pinout and timing constraints .sdc file that is not provided in the C29X_PCIE_DESIGN_FILES.zip download.  Otherwise, I would stand a good chance of screwing up the timing of the IFC address decode that occurs within the CPLD.

Is the .sdc for the C29X PCIE CPLD available?

[alexander_yakov]

Sorry for delayed response.

Here's what I got from the board designer:

Regarding to .sdc(time constraint file) , from my opinion, it is not neccesary for CPLD. Time constraint file is used for FPGA.

Have a great day,
Alexander
TIC

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[mikedubya]

Why can’t they just provide the Quartus project files used to build the CPLD, including any timing files?

If I download the provided oamp -v2.2.pof, my C29XPCIE board works fine. If I try rebuilding that .pof with the provided oamp -v2.2.v source file, it does not work. There is a timing difference on the read interface.

Reading the CPLD from u-boot using the original .pof looks like this:

=> md.b 0xFFFDF0000

ffdf0000: aa 55 40 40 00 00 00 00 00 00 00 00 00 00 00 00 .U@@............

ffdf0010: 00 02 e0 00 f0 00 60 00 00 00 00 00 00 00 00 00 ......`.........

With a rebuilt .pof, it looks like this:

=> md.b 0xFFFDF0000

ffdf0000: aa 00 00 00 00 c0 00 00 40 e0 00 00 00 60 00 00 ........@....`..

ffdf0010: 55 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 U.......@.......

Are you aware that there is an error in all revisions of the CPLD code? The 8-bit data bus (ifc_ad) port on the CPLD has an inverted bit order from the 8-bit IFC data bus from the processor.

For instance, U-Boot reports that the CPLD Version is 0x40, when really it should be 0x02 as U-boot is reading the CPLD SW Version register (0x03):

U-Boot 2016.012.0+ga9b437f (Feb 16 2017 - 17:14:34 -0500)

CPU: C293E, Version: 1.0, (0x85083010)

Core: e500, Version: 5.1, (0x80211151)

Clock Configuration:

CPU0:1200 MHz,

CCB:400 MHz,

DDR:600 MHz (1200 MT/s data rate) (Asynchronous), IFC:100 MHz

L1: D-cache 32 KiB enabled

I-cache 32 KiB enabled

I2C: ready

Board: C293PCIe, CPLD Ver: 0x40

And if you want to turn on the LED on the board, you have to write the MSB of the LED CSR register (0x15) instead of the LSB as indicated in the source code and the CPLD documentation. Try it if you like. Here is the U-Boot command to make the LED on the board blink:

=> nm.b fffdf0015

ffdf0015: 00 ? 01 (LED does not blink)

ffdf0015: 00 ? 01 (LED does not blink)

ffdf0015: 00 ? 80 (LED blinks)

ffdf0015: 80 ? 00 (LED is turned off)

ffdf0015: 00 ? q

So I would really appreciate it if you could track down the project files used to build the original .pof for this CPLD so it can be rebuilt and corrected.