Address Pointers used by the Security Engineer (SEC)

[rjschirmer]

I am using the SEC on both the lx2160a and ls1043a (and will possibly on other SoCs in the future) and noticed that the Address Pointers are different between the two.  The most significant difference is the double word ordering when using 49-bit/40-bit addressing on the lx2160a and lx1043a respectively.  The lx2160a uses most-significant Dword followed by least-significant, and the ls1043a uses least-significant Dword followed by the most-significant.  This appears to be unrelated to the endianness of the engine as defined by SSTA[PLEND].

My question is: is there a way to tell which version of address pointers is being used by a SEC?  (e.g. SEC version range for each type of address pointers)

[LFGP]

You could use the PS register to stablish the length to 32 bits.

The information regarding SEC block is provided under NDA, so, please open a new private case and share your NDA

[rjschirmer]

The use case requires larger than 32-bit addressing, so setting MCFGR[PS] to use 32-bit addressing will not work for me.

Per your suggestion I've opened a new private case to address this.