B4860 sometimes assert RESET_REQ_B or HRESET_B during boot

[weiwangw]

We have a custom board that refer to the B4860QDS Evaluation Board. Recently, a error occured during the boot process.

There are two kind of abnormal  phenomenon:

1) After power up, there's nothing output from the serial COM, and I find the PIN HRESET_B of B4860 is always asserted, thouth the PORESET_B negated for a long time.

2) After power up, there is output from serial COM, and the log is same as normal. But, the RESET_REQ_B is always asserted, and the PHY(connect to SGMII) is unusable. I read the registers of DCFG, the attachment below is them. The DCFG registers indicate that RESET_REQ_B asserts for SerDes PLL does not lock. But I have measured the serdes clocks, all are OK.

No matter NOR flash boot or NAND flash boot, two situations above both occur sometimes. The RCW of the board is in the attachments below(bin format). So I wander what may cause this?

Thank you!

Original Attachment has been moved to: 17_serdes.txt.zip

Original Attachment has been moved to: 17_dcfg.txt.zip

Original Attachment has been moved to: 17_serdes2.txt.zip

Original Attachment has been moved to: RCW_2904_4SGMII_DDR1866_cpu1600_rev2.bin.zip

[lunminliang]

Hello Warn Wong,

In 17-serdes2.txt, it has

SerDes2_PLL2RSTCTL    0x06474020    0x0ffe0eb020`Physical cache - inhibited

The RST_DONE file is not set, shows SerDes2 PLL2 is not locked. Can you please check all clocks and configuration about about this?

Regards

Lunmin

[weiwangw]

Thanks for your advice, Lunmin.

I delay the time that PBI and RCW load, and the two abnormal  phenomenons disappared. So, I guess that the time for serdes to lock isnt longer enough after power on.

Thank you!

[lunminliang]

Hello Warn Wong,

Good to know this and thanks for feedback.

Regards

Lunmin