Regarding device tree pin-mux calculation

[rahulM]

Hi NXP,

I was looking for pin-mux value to calculate from config tools for peripheral UART1 and SDIO.

I found some difference in value w.r.t to device tree and pin config tools for IMX8QM for cortex a-53 core0

In device tree for pin-AY48, AT44, AR43 and AV46 i.e for

AV46-SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
AR43-SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
AT44-SC_P_UART1_RX_DMA_UART1_RX 0x06000020
AY48-SC_P_UART1_TX_DMA_UART1_TX 0x06000020

device tree file entry

pinctrl_lpuart1: lpuart1grp {
    fsl,pins = <
        IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020
        IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020
        IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
        IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
   >;
 };

and in pin-mux config tool i am getting value for above as

AY48-SC_P_UART1_TX_DMA_UART1_TX  0x00000040

The value for AY48 is different in config tool and from device tree.

I am not able to understand the difference between this two and similar for all the pins like AT44, AR43 and AV46.

Device tree file is imx8qm-mek.dts and BSP yocto version-5.4.47_2.2.0 Release.

Please let me know how to calculate the pin-mux value manually and in the tool.

Thanks and Regards

Subramanya N M

[jamesbone]

The different positions it is because the Pins Balls for the UART  pins are in different locations, you need to review the IOMUXC registers in order to get options available in your package.  It is not an easy task to do it manually because you need to consider a matrix with all the balls of the package.

Thats why we recommend to use the PINS TOOL to select the positions that you would like to use in the package that you are going to use.