GD3160 watchdog fault (WDOG_FLT) cannot be cleared

[bkreger]

We are working on a project that uses six (6) GD3160 ICs and are currently working to get the devices initialized and configured. Specifically, we have implemented the power-up sequence provided in the Data Sheet (rev 11.0).

After powering the high-voltage domain (step 4a), and attempting to clear faults, the watchdog faults remain enabled (the watchdog fault is asserted on all 6 GD3160s).  A check of power supply voltages show that these are within acceptable ranges (we do not get faults for VSUP, VDD, VCC, or VREF either).

The data sheet says the following:  "A watchdog fault will latch when VSUP, VDD, VCC, or VREF falls below POR threshold voltage levels and exceeds the programmable watchdog timeout duration."  Are there any other conditions which would cause a watchdog fault to occur?

[guoweisun]

If CSB signal is low for a longer period than Watchdog time out, a watchdog fault

(WDOG_FLT) will be reported.

[bkreger]

Thanks for the quick response to my question.  I have some additional data for this issue.

Attached is a logic analyzer screen capture of the SPI communication to the GD3160s (in GD3160-SPI-Chain-Signals.png).  It shows that for a transmit to the three-device chain the chip select is active (low) for 9.4 us.  We checked this for multiple transmits and verified that it does not deviate much from this value (10s of ns).

Also, we have measured the voltages on the GD3160 voltage supply rails. They all look stable as shown in the attached file (pdf below).

Any thoughts on what the cause could be?

Thank you.

[bkreger]

Further information:
INTA is high
INTB is low
PWM signals are all low
FSENB is high

[guoweisun]

For the power up sequency, you can try to power on high voltage firstly then next power on the low voltage for GN3160.