Hopefully you found the power sequencing in section 2 of the HW spec? It's not spec'd as delay - it has to do with the ramp up time. The core voltage has to be at 90% (i.e. 0.9V ) before I/O voltage reaches 10% of it's value.
And as for the 1.0V stability - the requirement is driven by clock and is specified as requirement for reset held low while you have a stable clock (table 11 in the Spec I'm using). The requirement listed there is 32 clocks. So, basically 32 clocks after power is stable and clock is stable, you can release PORESET.
... Paul
