Is it correct that TIMING_CFG_5[RODT_ON] and TIMING_CFG_5[RODT_OFF] do not affect internal ODT circuit for MPC8535? These values are always set in u-boot for our DDR3 based boards (e.g. P2020DS, MPC8569MDS). However external ODT is never enabled for SDRAM reads, this could lead to a conclusion that internal ODT is also affected by the TIMING_CFG_5 setting. Can you comment? TIMING_CFG_5 register is only for DRAM ODT (external ODT), this is verified and confirmed. As for your suggestion that because in most cases the read ODT on DRAM is off and hence it has something to do with internal ODT is not a valid assumption. The Read ODT for DRAM is an option available if required. In most cases it will not apply, but there may be a configuration that may require it and then the option is available for such users. Please clarify the meaning of TIMING_CFG_5 register for DDR3 controller of the MPC8535. The sentence ".. relevant ODT signal(s)" is common to all fields. What is this referring to? Is that both a) an internal signal controlling internal IOs (enabled by CFG_2[ODT_CFG]) and b) the external MODT[] signals going to the SDRAM? If yes, what is the delay between the assertion of the internal ODT signal (e.g. set by TIMING_CFG_5[RODT_ON])and actual switching of the internal RTT? These are related to the ODT timings to the DRAM. If ODT during reads is not used, then the RODT_ON and RODT_OFF values can be cleared. These are the ODT signal turn ON/OFF latency. For DDR3 it is defined as WL-2=CWL+AL-2. If one DIMM slot is used then there is no need for dynamic ODT setting.

For MPC8360, is any way that the CPU can read and write the full 72-bit wide DDR memory bus, bypassing the ECC logic? I want to know if the memory controller can be configured for the 72-bit wide DDR memory bus to bypass the ECC logic. It is not possible to bypass the ECC and read/write using full 72-bit wide bus. The controller uses the last byte lane to generate ECC info and cannot be bypassed. For MPC8360 DDR SDRAM refresh, can you please advise how to "exactly" calculate the appropriate value of [REFINT] if such worst case scenario in which refresh command issue timing is postponed is taken into account? The refresh interval should be set as high as allowable by the DRAM specifications. This should be calculated by using tREFI in the DRAM specifications, which may depend upon the operating temperature of the DRAM. In addition, to allow a memory transaction in progress to be completed when the refresh interval is reached and not violating the device refresh period, set the REFINT value to a value less than that calculated by using tREFI. The value selected for REFINT could be larger than tREFI if the DDR_SDRAM_CFG[NUM_PR] has a value higher than 1. To calculate the max possible value when DDR_SDRAM_CFG[NUM_PR] is higher than 1, use the following formula: (tREFI/clk period) x (NUM_PR) = REFINT A timing tDISKEW (skew between MDQS and MDQ) is depicted in DDR2 and DDR3 SDRAM Interface Input Timing Diagram in MPC8360 Hardware spec. For measuring tDISKEW, please instruct me from which point of the MDQS waveform and to which point of MDQ waveform should be measured? For measuring MDQS, it should be at the cross point. For case of MDQ it is derated to the VREF. Why does MCK to MDQS Skew tDDKHMH has such a high value of +/-525ps for DDR3 800M data rate for MPC8360? I am afraid that write-leveling can NOT remove all internal MCK to MDQS skew from tDDKHMH. Can you please let me know how much internal skew will be removed after write-leveling? tDDKHMH value of +/-525ps for MPC8360 part is a conservative value in the HW spec. For DDR3 with write leveling enabled, this AC timing parameter would be a non-factor.

Is there any suggested approach to determining the tx/rx ring buffer sizes on the peripherals that interface to the UCC? How can I decide on the ring size? The bandwidth would be 45 Mbps. The MTU on the serial interface can range up to 16k Bytes. Even if MTU could be 16K bytes, the average frame could be much smaller. Find out the average frame size and pick up a buffer size that is bit larger than the average frame size. This usually creates a good balance of efficiency between processing time and memory usage. It is much more efficient in terms of processing time to process a frame of 16K in one BD/Buffer of 16K size than in 16 BDs/Buffers of 1K size. However, if all buffers are 16K size while 90% of the frames are 1K, most memory is wasted. Generally, the ring size should be equal to the number of BD’s required to accommodate the largest possible frame size + 4 extra BDs. However, over here the bandwidth is relatively high (45M) and could be quite bursty. Hence we would suggest starting with "TWO largest possible frame size + 4 extra BDs" P1016 Hardware spec says that the QUICC engine periodically polls its Rx/Tx rings and if a BD is not empty, checks the ownership flag and moves to the next step. How does the user application trigger/control the QE to start polling? For TX BD ring, (after configured) QE will periodically poll the ring and process the BD that is not empty and then move to next BD. When a BD is actually transmitted, a "transmission complete" event (and interrupt if enabled) will be generated, so the BD/Buffer can be released. For RX BD ring, (after configured) QE will pre-fetch a BD and then process the BD when data is received. When a packet (frame) is received, a "received" event (and interrupt if enabled) will be generated, so the BD/Buffer can be released/processed. If no empty BD is available during the pre-fetch, an "out-of-BD" error will be reported. After MPC8306 QE reset, when cores enables transmitter but BD is not ready, what signal will be on the line - IDLE(0XFF) or flags(7E)? Can this signal be configured? Yes, it should be configured by GUMR[RTSM].

Does MPC8306 come with SerDes clocks enabled? Will MPC8306 remain in reset if the SERDES is enabled and no SerDes reference clock is available? Yes, MPC8306 comes with SerDes clocks enabled. However, MPC8306 doesn't wait for SERDES PLL lock for it to come out of reset. For MPC8306, which jitter spec (tCLK_DJ, tCLK_TJ or tCLK_DJ+tCLK_TJ) should the buffer and oscillator require to meet? The input jitter at the SD_REF CLK input is specified, Buffer vendor will have to provide jitter at the output in pk-to-pk terms so that it can be compared with the Tj at SD_REF CLK input What is the relationship between RMS jitter and peak-to-peak jitter in MPC8306? How can I calculate the RMS jitter value from our peak-to-peak jitter value (42 ps and 86 ps)? RMS jitter is only valid for Random (Gaussian distribution) jitter. This rms value is then converted to pk-to-pk value and added to Deterministic jitter (pk-to-pk) for finding the total jitter (in pk-to-pk). For SD_REF CLK, the HW specs state the value for Total jitter (in peak to peak ps) and Deterministic jitter (in peak to peak ps). rms value for Rj can be referred from PCI Express™ Jitter and BER Revision 1.0. Converting the rms to pk-to-pk is not going to help here because the buffer datasheet states the additive phase jitter. This is measured by integrating the phase noise over the frequency band of interest. DDR. “In asynchronous mode, the memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR PLL rate." Is this statement correct for MPC8306? No it is not correct. The correct statement is " In asynchronous mode, if the ratio of the DDR data rate to the CCB clock rate is greater than 3 :1 ( i.e. DDR=3:CCB=1 ), than the DDR performance monitor statistic accuracy cannot be guaranteed."

Please specify the DDR read only and write only counters for MPC8308. Event 19 counts DDR reads only while event 27 counts DDR writes only in MPC8308. How are DDR errors cleared in the ESUMR reg (bit 8)? Do they need to re-init the DDR? You need to clear the ERR_DEFECT [MBE] bit (write 1 to clear). After that the ESUMR bit 8 will be cleared.

MPC8535 PCI controller can get clock from SYSCLK (synchronous) or from PCICLK (PCI asynchronous mode). If PCI is configured as PCI asynchronous mode, a valid clock must be provided on pin PCICLK, otherwise the processor will not boot up. Is this limit just due to PCI bus specs and if PCI is not used then MPC8535 PCI block can withstand 125MHz in synchronous mode? The PCI input clock frequency spec range is between 33 - 66MHz. IF the PCI interface is enabled, then this spec here will matter regardless whether you are running in synchronous or asynchronous mode. IF the PCI is disabled / un-used, it will not matter what input clock is being fed into this interface. Also, please refer to section 15.2 of the 8535 bring-up guide for termination details of the PCI pins including the PCI1_CLK pin when the interface is not being used. I am starting 8535 design making use of both SerDes serial interfaces: 1) SerDes1: PCI Express 1 (x4) (2.5 Gbps) → SerDes1 Lanes A-D; PCI Express 2 (x1) (2.5 Gbps) → SerDes1 Lanes E-F 2) SerDes2: SATA1 → SerDes2 Lane A. Each SerDes has its own reference clock. They will both run at 100MHz. Are there any phase requirements between these 2 clocks? There is no requirement on 8535 for any particular phase relationship between reference clock for Serdes 1 vs Serdes 2 because each serdes is completely independent.

For MPC8308 package, which is the GTX clock pin for TSEC1 and TSEC2? According to the MPC8308 ballmap, V21 is the GTX clock pin of TSEC1 and T19 is the GTX clock pin of TSEC2. Can a spread spectrum clock be used for the 66.66 Mhz DDR clock of the MPC8308? If so what percentage spread is allowed and what modulation frequency? Yes, a spread spectrum clock can be used for 66.66 Mhz DDR clock. Please refer to below table for details: Spread Spectrum Clock Source Recommendations Parameter Min Max Unit Frequency modulation — 60 kHz Frequency spread — 1.0  %

Please confirm that a PCIe lane on the MPC8308 can be enabled after POR (configured off in h/w but turned on in s/w). If so how this would be implemented? It is possible to control PCIe Lane turned on through s/w. You can control this through SRDSCR2 [0:7]. Through this control you can power -up or power- down individual lanes separately What is the difference between two strap options for PCIe ports - 0b00 or 0b11? In terms of PCIe, options 0b00 and 0b11 are redundant, but in terms of SGMII, they are different 0b00 - 2 lanes are for PCIe; the remaining 2 lanes are powered down 0b11 - 2 lanes are for PCIe; the remaining 2 lanes are for SGMII 0b01 - 3 lanes are for PCIe; the remaining 1 lane is powered down 0b10 - 3 lanes are for PCIe; the remaining 1 lane is for SGMII When SGMII is not used, the corresponding lane(s) should be powered down to save power.

MPC8360 H/W spec describes that Max SYSCLK frequency is 100MHz. Generically when user inputs 100MHz clock, actual clock speed become more faster. I think MPC8360 has enough margin for faster SYSCLK as long as I use up to 100MHz oscillator. Is my understanding correct? Yes, your understanding is correct. As long as you use 100MHz oscillator it should be fine.