KITPF8200FRDPGM error

[jjaa]

i use KITPF8200FRDPGM and MC33PF8200

TBB Mode is Possibe But OTP Mode is not possible

here is my script 

OTP:

SET_DPIN:PF8200:PWRON:low
SET_DPIN:PF8200:WDI:low
SET_DPIN:PF8200:TBBEN:high
SET_DPIN:PF8200:USBEN:high
SET_DPIN:PF8200:BSTEN:high
SET_DPIN:PF8200:VDDOTPEN:high
SET_REG:PF8200:OTP_MIRROR:OTP_FSOB_SELECT:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_I2C:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_CTRL1:0x0A
SET_REG:PF8200:OTP_MIRROR:OTP_CTRL2:0x41
SET_REG:PF8200:OTP_MIRROR:OTP_CTRL3:0x41
SET_REG:PF8200:OTP_MIRROR:OTP_FREQ_CTRL:0x80
SET_REG:PF8200:OTP_MIRROR:OTP_COINCELL_CTRL:0x0B
SET_REG:PF8200:OTP_MIRROR:OTP_PWRON:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_WD_CONFIG:0x10
SET_REG:PF8200:OTP_MIRROR:OTP_WD_EXPIRE:0x07
SET_REG:PF8200:OTP_MIRROR:OTP_WD_COUNTER:0xAF
SET_REG:PF8200:OTP_MIRROR:OTP_FAULT_COUNTER:0xF0
SET_REG:PF8200:OTP_MIRROR:OTP_FAULT_TIMERS:0x7F
SET_REG:PF8200:OTP_MIRROR:OTP_PWRDN_DLY1:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_PWRDN_DLY2:0x81
SET_REG:PF8200:OTP_MIRROR:OTP_PWRUP_CTRL:0x02
SET_REG:PF8200:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_PGOOD_PWRUP:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_SW1_VOLT:0x20
SET_REG:PF8200:OTP_MIRROR:OTP_SW1_PWRUP:0x15
SET_REG:PF8200:OTP_MIRROR:OTP_SW1_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW1_CONFIG2:0x09
SET_REG:PF8200:OTP_MIRROR:OTP_SW2_VOLT:0x70
SET_REG:PF8200:OTP_MIRROR:OTP_SW2_PWRUP:0x15
SET_REG:PF8200:OTP_MIRROR:OTP_SW2_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW2_CONFIG2:0x29
SET_REG:PF8200:OTP_MIRROR:OTP_SW3_VOLT:0x60
SET_REG:PF8200:OTP_MIRROR:OTP_SW3_PWRUP:0x3D
SET_REG:PF8200:OTP_MIRROR:OTP_SW3_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW3_CONFIG2:0x3B
SET_REG:PF8200:OTP_MIRROR:OTP_SW4_VOLT:0xB1
SET_REG:PF8200:OTP_MIRROR:OTP_SW4_PWRUP:0x47
SET_REG:PF8200:OTP_MIRROR:OTP_SW4_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW4_CONFIG2:0x2B
SET_REG:PF8200:OTP_MIRROR:OTP_SW5_VOLT:0xB0
SET_REG:PF8200:OTP_MIRROR:OTP_SW5_PWRUP:0x51
SET_REG:PF8200:OTP_MIRROR:OTP_SW5_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW5_CONFIG2:0x33
SET_REG:PF8200:OTP_MIRROR:OTP_SW6_VOLT:0x38
SET_REG:PF8200:OTP_MIRROR:OTP_SW6_PWRUP:0x51
SET_REG:PF8200:OTP_MIRROR:OTP_SW6_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW6_CONFIG2:0x13
SET_REG:PF8200:OTP_MIRROR:OTP_SW7_VOLT:0x15
SET_REG:PF8200:OTP_MIRROR:OTP_SW7_PWRUP:0x47
SET_REG:PF8200:OTP_MIRROR:OTP_SW7_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW7_CONFIG2:0x03
SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_VOLT:0x52
SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_PWRUP:0x5B
SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_CONFIG:0x06
SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_VOLT:0x50
SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_PWRUP:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_CONFIG:0x12
SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_VOLT:0x52
SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_PWRUP:0x65
SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_CONFIG:0x06
SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_VOLT:0x52
SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_PWRUP:0x6F
SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_CONFIG:0x06
SET_REG:PF8200:OTP_MIRROR:OTP_VSNVS_CONFIG:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_OV_BYPASS1:0x7F
SET_REG:PF8200:OTP_MIRROR:OTP_OV_BYPASS2:0x0F
SET_REG:PF8200:OTP_MIRROR:OTP_UV_BYPASS1:0x7F
SET_REG:PF8200:OTP_MIRROR:OTP_UV_BYPASS2:0x0F
SET_REG:PF8200:OTP_MIRROR:OTP_ILIM_BYPASS1:0x7F
SET_REG:PF8200:OTP_MIRROR:OTP_ILIM_BYPASS2:0x0F
SET_REG:PF8200:OTP_MIRROR:OTP_PROG_IDH:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_PROG_IDL:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_DEBUG1:0x01
SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP1:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP2:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP3:0x00

// CONFIGURE OTP CONTROLLER
SET_REG:PF8200:OTP_PAGE2:FCMD:0x80
SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x00
SET_REG:PF8200:OTP_PAGE2:FDATA:0xAC
SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9
SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x02
SET_REG:PF8200:OTP_PAGE2:FDATA:0xDC
SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9
SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x08
SET_REG:PF8200:OTP_PAGE2:FDATA:0x38
SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9
SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x09
SET_REG:PF8200:OTP_PAGE2:FDATA:0xDC
SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9
SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x0C
SET_REG:PF8200:OTP_PAGE2:FDATA:0xD2
SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9

SET_REG:PF8200:OTP_PAGE2:MAX_PGM_TRIES:0x08
SET_REG:PF8200:OTP_PAGE2:MRR_SVDR_IN:0x13
SET_REG:PF8200:OTP_PAGE2:MR_TEST_H:0x00
SET_REG:PF8200:OTP_PAGE2:MR_TEST_L:0x02
SET_REG:PF8200:OTP_PAGE2:MREF_TEST_H:0x00
SET_REG:PF8200:OTP_PAGE2:MREF_TEST_L:0x00
SET_REG:PF8200:OTP_PAGE2:PULSE_DUR_1:0xBB
SET_REG:PF8200:OTP_PAGE2:PULSE_DUR_2:0x08
SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x00
SET_REG:PF8200:OTP_PAGE2:FADDR_STOP:0x48

// SET CRC VALUES
SET_REG:PF8200:OTP_PAGE2:FCMD:0xA5
SET_REG:PF8200:OTP_PAGE2:FCMD:0xA4
GET_REG:PF8200:OTP_MIRROR:OTP_S0_CRC_LSB
GET_REG:PF8200:OTP_MIRROR:OTP_S0_CRC_MSB
GET_REG:PF8200:OTP_PAGE2:SECT_STATUS

// START FUSE PROGRAMMING
SET_REG:PF8200:OTP_PAGE2:FCMD:0x96
GET_REG:PF8200:OTP_PAGE2:FSTATUS
GET_REG:PF8200:OTP_PAGE2:FSTATUS
GET_REG:PF8200:OTP_PAGE2:FSTATUS
GET_REG:PF8200:OTP_PAGE2:FSTATUS
GET_REG:PF8200:OTP_PAGE2:FSTATUS
GET_REG:PF8200:OTP_PAGE2:FSTATUS
GET_REG:PF8200:OTP_PAGE2:FSTATUS
GET_REG:PF8200:OTP_PAGE2:FSTATUS

// BURN BOOT ENABLE AND WRITE PROTECT BITS
SET_REG:PF8200:OTP_PAGE2:FADDR_STOP:0xFF
SET_REG:PF8200:OTP_PAGE2:FADDR_START:0xFE
SET_REG:PF8200:OTP_PAGE2:FDATA:0xAA
SET_REG:PF8200:OTP_PAGE2:FCMD:0x87
GET_REG:PF8200:OTP_PAGE2:FSTATUS
GET_REG:PF8200:OTP_PAGE2:FSTATUS
SET_REG:PF8200:OTP_PAGE2:FADDR_START:0xFF
SET_REG:PF8200:OTP_PAGE2:FDATA:0x55
SET_REG:PF8200:OTP_PAGE2:FCMD:0x87
GET_REG:PF8200:OTP_PAGE2:FSTATUS
GET_REG:PF8200:OTP_PAGE2:FSTATUS
SET_REG:PF8200:OTP_PAGE2:FADDR_START:0xFC
SET_REG:PF8200:OTP_PAGE2:FDATA:0xAA
SET_REG:PF8200:OTP_PAGE2:FCMD:0x87
GET_REG:PF8200:OTP_PAGE2:FSTATUS
GET_REG:PF8200:OTP_PAGE2:FSTATUS
SET_REG:PF8200:OTP_PAGE2:FADDR_START:0xFD
SET_REG:PF8200:OTP_PAGE2:FDATA:0x55
SET_REG:PF8200:OTP_PAGE2:FCMD:0x87
GET_REG:PF8200:OTP_PAGE2:FSTATUS
GET_REG:PF8200:OTP_PAGE2:FSTATUS
GET_REG:PF8200:OTP_PAGE2:SECT_STATUS

SET_DPIN:PF8200:USBEN:low
SET_DPIN:PF8200:BSTEN:low
SET_DPIN:PF8200:VDDOTPEN:low

//Verify Mirror Registers = Fuse Value
GET_REG:PF8200:functional:DEVICE_ID
SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x00
SET_REG:PF8200:OTP_PAGE2:FADDR_STOP:0x48
SET_REG:PF8200:OTP_PAGE2:FCMD:0xAB
SET_REG:PF8200:OTP_PAGE2:FCMD:0xA0
SET_REG:PF8200:OTP_PAGE2:FCMD:0xA1
SET_REG:PF8200:OTP_PAGE2:FCMD:0xA4
GET_REG:PF8200:OTP_MIRROR:OTP_S0_CRC_LSB
GET_REG:PF8200:OTP_MIRROR:OTP_S0_CRC_MSB
GET_REG:PF8200:OTP_PAGE2:SECT_STATUS
GET_REG:PF8200:OTP_PAGE2:FSTATUS

//If SECT_STATUS = 0x3F & FSTATUS = 0x00 part is programmed correctly.
//Verify CRC_LSB and CRC_MSB match the values in section "SET CRC VALUES" .
SET_DPIN:PF8200:TBBEN:low

TBB:

SET_DPIN:PF8200:PWRON:low
SET_DPIN:PF8200:WDI:low
SET_DPIN:PF8200:TBBEN:high
SET_REG:PF8200:OTP_MIRROR:OTP_FSOB_SELECT:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_I2C:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_CTRL1:0x0A
SET_REG:PF8200:OTP_MIRROR:OTP_CTRL2:0x41
SET_REG:PF8200:OTP_MIRROR:OTP_CTRL3:0x41
SET_REG:PF8200:OTP_MIRROR:OTP_FREQ_CTRL:0x80
SET_REG:PF8200:OTP_MIRROR:OTP_COINCELL_CTRL:0x0B
SET_REG:PF8200:OTP_MIRROR:OTP_PWRON:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_WD_CONFIG:0x10
SET_REG:PF8200:OTP_MIRROR:OTP_WD_EXPIRE:0x07
SET_REG:PF8200:OTP_MIRROR:OTP_WD_COUNTER:0xAF
SET_REG:PF8200:OTP_MIRROR:OTP_FAULT_COUNTER:0xF0
SET_REG:PF8200:OTP_MIRROR:OTP_FAULT_TIMERS:0x7F
SET_REG:PF8200:OTP_MIRROR:OTP_PWRDN_DLY1:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_PWRDN_DLY2:0x81
SET_REG:PF8200:OTP_MIRROR:OTP_PWRUP_CTRL:0x02
SET_REG:PF8200:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_PGOOD_PWRUP:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_SW1_VOLT:0x20
SET_REG:PF8200:OTP_MIRROR:OTP_SW1_PWRUP:0x15
SET_REG:PF8200:OTP_MIRROR:OTP_SW1_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW1_CONFIG2:0x09
SET_REG:PF8200:OTP_MIRROR:OTP_SW2_VOLT:0x70
SET_REG:PF8200:OTP_MIRROR:OTP_SW2_PWRUP:0x15
SET_REG:PF8200:OTP_MIRROR:OTP_SW2_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW2_CONFIG2:0x29
SET_REG:PF8200:OTP_MIRROR:OTP_SW3_VOLT:0x60
SET_REG:PF8200:OTP_MIRROR:OTP_SW3_PWRUP:0x3D
SET_REG:PF8200:OTP_MIRROR:OTP_SW3_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW3_CONFIG2:0x3B
SET_REG:PF8200:OTP_MIRROR:OTP_SW4_VOLT:0xB1
SET_REG:PF8200:OTP_MIRROR:OTP_SW4_PWRUP:0x47
SET_REG:PF8200:OTP_MIRROR:OTP_SW4_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW4_CONFIG2:0x2B
SET_REG:PF8200:OTP_MIRROR:OTP_SW5_VOLT:0xB0
SET_REG:PF8200:OTP_MIRROR:OTP_SW5_PWRUP:0x51
SET_REG:PF8200:OTP_MIRROR:OTP_SW5_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW5_CONFIG2:0x33
SET_REG:PF8200:OTP_MIRROR:OTP_SW6_VOLT:0x38
SET_REG:PF8200:OTP_MIRROR:OTP_SW6_PWRUP:0x51
SET_REG:PF8200:OTP_MIRROR:OTP_SW6_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW6_CONFIG2:0x13
SET_REG:PF8200:OTP_MIRROR:OTP_SW7_VOLT:0x15
SET_REG:PF8200:OTP_MIRROR:OTP_SW7_PWRUP:0x47
SET_REG:PF8200:OTP_MIRROR:OTP_SW7_CONFIG1:0x53
SET_REG:PF8200:OTP_MIRROR:OTP_SW7_CONFIG2:0x03
SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_VOLT:0x52
SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_PWRUP:0x5B
SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_CONFIG:0x06
SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_VOLT:0x50
SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_PWRUP:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_CONFIG:0x12
SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_VOLT:0x52
SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_PWRUP:0x65
SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_CONFIG:0x06
SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_VOLT:0x52
SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_PWRUP:0x6F
SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_CONFIG:0x06
SET_REG:PF8200:OTP_MIRROR:OTP_VSNVS_CONFIG:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_OV_BYPASS1:0x7F
SET_REG:PF8200:OTP_MIRROR:OTP_OV_BYPASS2:0x0F
SET_REG:PF8200:OTP_MIRROR:OTP_UV_BYPASS1:0x7F
SET_REG:PF8200:OTP_MIRROR:OTP_UV_BYPASS2:0x0F
SET_REG:PF8200:OTP_MIRROR:OTP_ILIM_BYPASS1:0x7F
SET_REG:PF8200:OTP_MIRROR:OTP_ILIM_BYPASS2:0x0F
SET_REG:PF8200:OTP_MIRROR:OTP_PROG_IDH:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_PROG_IDL:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_DEBUG1:0x01
SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP1:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP2:0x00
SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP3:0x00
SET_REG:PF8200:OTP_PAGE2:FCMD:0xA5
SET_REG:PF8200:OTP_PAGE2:FCMD:0xA4
SET_REG:PF8200:functional:TEST_FLAGS:0x07
SET_DPIN:PF8200:TBBEN:low
SET_DPIN:PF8200:PWRON:high

OTP Result:

OK: set PWRON digital pin = LOW
OK: set WDI digital pin = LOW
OK: set TBBEN digital pin = HIGH
OK: set USBEN digital pin = HIGH
OK: set BSTEN digital pin = HIGH
OK: set VDDOTPEN digital pin = HIGH
OK: write reg. OTP_FSOB_SELECT = 0x00
OK: write reg. OTP_I2C = 0x00
OK: write reg. OTP_CTRL1 = 0x0a
OK: write reg. OTP_CTRL2 = 0x41
OK: write reg. OTP_CTRL3 = 0x41
OK: write reg. OTP_FREQ_CTRL = 0x80
OK: write reg. OTP_COINCELL_CTRL = 0x0b
OK: write reg. OTP_PWRON = 0x00
OK: write reg. OTP_WD_CONFIG = 0x10
OK: write reg. OTP_WD_EXPIRE = 0x07
OK: write reg. OTP_WD_COUNTER = 0xaf
OK: write reg. OTP_FAULT_COUNTER = 0xf0
OK: write reg. OTP_FAULT_TIMERS = 0x7f
OK: write reg. OTP_PWRDN_DLY1 = 0x00
OK: write reg. OTP_PWRDN_DLY2 = 0x81
OK: write reg. OTP_PWRUP_CTRL = 0x02
OK: write reg. OTP_RESETBMCU_PWRUP = 0x00
OK: write reg. OTP_PGOOD_PWRUP = 0x00
OK: write reg. OTP_SW1_VOLT = 0x20
OK: write reg. OTP_SW1_PWRUP = 0x15
OK: write reg. OTP_SW1_CONFIG1 = 0x53
OK: write reg. OTP_SW1_CONFIG2 = 0x09
OK: write reg. OTP_SW2_VOLT = 0x70
OK: write reg. OTP_SW2_PWRUP = 0x15
OK: write reg. OTP_SW2_CONFIG1 = 0x53
OK: write reg. OTP_SW2_CONFIG2 = 0x29
OK: write reg. OTP_SW3_VOLT = 0x60
OK: write reg. OTP_SW3_PWRUP = 0x3d
OK: write reg. OTP_SW3_CONFIG1 = 0x53
OK: write reg. OTP_SW3_CONFIG2 = 0x3b
OK: write reg. OTP_SW4_VOLT = 0xb1
OK: write reg. OTP_SW4_PWRUP = 0x47
OK: write reg. OTP_SW4_CONFIG1 = 0x53
OK: write reg. OTP_SW4_CONFIG2 = 0x2b
OK: write reg. OTP_SW5_VOLT = 0xb0
OK: write reg. OTP_SW5_PWRUP = 0x51
OK: write reg. OTP_SW5_CONFIG1 = 0x53
OK: write reg. OTP_SW5_CONFIG2 = 0x33
OK: write reg. OTP_SW6_VOLT = 0x38
OK: write reg. OTP_SW6_PWRUP = 0x51
OK: write reg. OTP_SW6_CONFIG1 = 0x53
OK: write reg. OTP_SW6_CONFIG2 = 0x13
OK: write reg. OTP_SW7_VOLT = 0x15
OK: write reg. OTP_SW7_PWRUP = 0x47
OK: write reg. OTP_SW7_CONFIG1 = 0x53
OK: write reg. OTP_SW7_CONFIG2 = 0x03
OK: write reg. OTP_LDO1_VOLT = 0x52
OK: write reg. OTP_LDO1_PWRUP = 0x5b
OK: write reg. OTP_LDO1_CONFIG = 0x06
OK: write reg. OTP_LDO2_VOLT = 0x50
OK: write reg. OTP_LDO2_PWRUP = 0x00
OK: write reg. OTP_LDO2_CONFIG = 0x12
OK: write reg. OTP_LDO3_VOLT = 0x52
OK: write reg. OTP_LDO3_PWRUP = 0x65
OK: write reg. OTP_LDO3_CONFIG = 0x06
OK: write reg. OTP_LDO4_VOLT = 0x52
OK: write reg. OTP_LDO4_PWRUP = 0x6f
OK: write reg. OTP_LDO4_CONFIG = 0x06
OK: write reg. OTP_VSNVS_CONFIG = 0x00
OK: write reg. OTP_OV_BYPASS1 = 0x7f
OK: write reg. OTP_OV_BYPASS2 = 0x0f
OK: write reg. OTP_UV_BYPASS1 = 0x7f
OK: write reg. OTP_UV_BYPASS2 = 0x0f
OK: write reg. OTP_ILIM_BYPASS1 = 0x7f
OK: write reg. OTP_ILIM_BYPASS2 = 0x0f
OK: write reg. OTP_PROG_IDH = 0x00
OK: write reg. OTP_PROG_IDL = 0x00
OK: write reg. OTP_DEBUG1 = 0x01
OK: write reg. OTP_SW_COMP1 = 0x00
OK: write reg. OTP_SW_COMP2 = 0x00
OK: write reg. OTP_SW_COMP3 = 0x00

// CONFIGURE OTP CONTROLLER
OK: write reg. FCMD = 0x80
OK: write reg. FADDR_START = 0x00
OK: write reg. FDATA = 0xac
OK: write reg. FCMD = 0xa9
OK: write reg. FADDR_START = 0x02
OK: write reg. FDATA = 0xdc
OK: write reg. FCMD = 0xa9
OK: write reg. FADDR_START = 0x08
OK: write reg. FDATA = 0x38
OK: write reg. FCMD = 0xa9
OK: write reg. FADDR_START = 0x09
OK: write reg. FDATA = 0xdc
OK: write reg. FCMD = 0xa9
OK: write reg. FADDR_START = 0x0c
OK: write reg. FDATA = 0xd2
OK: write reg. FCMD = 0xa9

OK: write reg. MAX_PGM_TRIES = 0x08
OK: write reg. MRR_SVDR_IN = 0x13
OK: write reg. MR_TEST_H = 0x00
OK: write reg. MR_TEST_L = 0x02
OK: write reg. MREF_TEST_H = 0x00
OK: write reg. MREF_TEST_L = 0x00
OK: write reg. PULSE_DUR_1 = 0xbb
OK: write reg. PULSE_DUR_2 = 0x08
OK: write reg. FADDR_START = 0x00
OK: write reg. FADDR_STOP = 0x48

// SET CRC VALUES
OK: write reg. FCMD = 0xa5
OK: write reg. FCMD = 0xa4
Error: Command execution failed
Error: Command execution failed
Error: Command execution failed

// START FUSE PROGRAMMING
OK: write reg. FCMD = 0x96
Error: Command execution failed
Error: Command execution failed
Error: Command execution failed
Error: Command execution failed
Error: Command execution failed
Error: Command execution failed
Error: Command execution failed
Error: Command execution failed

// BURN BOOT ENABLE AND WRITE PROTECT BITS
OK: write reg. FADDR_STOP = 0xff
OK: write reg. FADDR_START = 0xfe
OK: write reg. FDATA = 0xaa
OK: write reg. FCMD = 0x87
Error: Command execution failed
Error: Command execution failed
OK: write reg. FADDR_START = 0xff
OK: write reg. FDATA = 0x55
OK: write reg. FCMD = 0x87
Error: Command execution failed
Error: Command execution failed
OK: write reg. FADDR_START = 0xfc
OK: write reg. FDATA = 0xaa
OK: write reg. FCMD = 0x87
Error: Command execution failed
Error: Command execution failed
OK: write reg. FADDR_START = 0xfd
OK: write reg. FDATA = 0x55
OK: write reg. FCMD = 0x87
Error: Command execution failed
Error: Command execution failed
Error: Command execution failed

OK: set USBEN digital pin = LOW
OK: set BSTEN digital pin = LOW
OK: set VDDOTPEN digital pin = LOW

//Verify Mirror Registers = Fuse Value
Error: Command execution failed
OK: write reg. FADDR_START = 0x00
OK: write reg. FADDR_STOP = 0x48
OK: write reg. FCMD = 0xab
OK: write reg. FCMD = 0xa0
OK: write reg. FCMD = 0xa1
OK: write reg. FCMD = 0xa4
Error: Command execution failed
Error: Command execution failed
Error: Command execution failed
Error: Command execution failed

//If SECT_STATUS = 0x3F & FSTATUS = 0x00 part is programmed correctly.
//Verify CRC_LSB and CRC_MSB match the values in section "SET CRC VALUES" .
OK: set TBBEN digital pin = LOW

TBB result:

OK: set PWRON digital pin = LOW
OK: set WDI digital pin = LOW
OK: set TBBEN digital pin = HIGH
OK: write reg. OTP_FSOB_SELECT = 0x00
OK: write reg. OTP_I2C = 0x00
OK: write reg. OTP_CTRL1 = 0x0a
OK: write reg. OTP_CTRL2 = 0x41
OK: write reg. OTP_CTRL3 = 0x41
OK: write reg. OTP_FREQ_CTRL = 0x80
OK: write reg. OTP_COINCELL_CTRL = 0x0b
OK: write reg. OTP_PWRON = 0x00
OK: write reg. OTP_WD_CONFIG = 0x10
OK: write reg. OTP_WD_EXPIRE = 0x07
OK: write reg. OTP_WD_COUNTER = 0xaf
OK: write reg. OTP_FAULT_COUNTER = 0xf0
OK: write reg. OTP_FAULT_TIMERS = 0x7f
OK: write reg. OTP_PWRDN_DLY1 = 0x00
OK: write reg. OTP_PWRDN_DLY2 = 0x81
OK: write reg. OTP_PWRUP_CTRL = 0x02
OK: write reg. OTP_RESETBMCU_PWRUP = 0x00
OK: write reg. OTP_PGOOD_PWRUP = 0x00
OK: write reg. OTP_SW1_VOLT = 0x20
OK: write reg. OTP_SW1_PWRUP = 0x15
OK: write reg. OTP_SW1_CONFIG1 = 0x53
OK: write reg. OTP_SW1_CONFIG2 = 0x09
OK: write reg. OTP_SW2_VOLT = 0x70
OK: write reg. OTP_SW2_PWRUP = 0x15
OK: write reg. OTP_SW2_CONFIG1 = 0x53
OK: write reg. OTP_SW2_CONFIG2 = 0x29
OK: write reg. OTP_SW3_VOLT = 0x60
OK: write reg. OTP_SW3_PWRUP = 0x3d
OK: write reg. OTP_SW3_CONFIG1 = 0x53
OK: write reg. OTP_SW3_CONFIG2 = 0x3b
OK: write reg. OTP_SW4_VOLT = 0xb1
OK: write reg. OTP_SW4_PWRUP = 0x47
OK: write reg. OTP_SW4_CONFIG1 = 0x53
OK: write reg. OTP_SW4_CONFIG2 = 0x2b
OK: write reg. OTP_SW5_VOLT = 0xb0
OK: write reg. OTP_SW5_PWRUP = 0x51
OK: write reg. OTP_SW5_CONFIG1 = 0x53
OK: write reg. OTP_SW5_CONFIG2 = 0x33
OK: write reg. OTP_SW6_VOLT = 0x38
OK: write reg. OTP_SW6_PWRUP = 0x51
OK: write reg. OTP_SW6_CONFIG1 = 0x53
OK: write reg. OTP_SW6_CONFIG2 = 0x13
OK: write reg. OTP_SW7_VOLT = 0x15
OK: write reg. OTP_SW7_PWRUP = 0x47
OK: write reg. OTP_SW7_CONFIG1 = 0x53
OK: write reg. OTP_SW7_CONFIG2 = 0x03
OK: write reg. OTP_LDO1_VOLT = 0x52
OK: write reg. OTP_LDO1_PWRUP = 0x5b
OK: write reg. OTP_LDO1_CONFIG = 0x06
OK: write reg. OTP_LDO2_VOLT = 0x50
OK: write reg. OTP_LDO2_PWRUP = 0x00
OK: write reg. OTP_LDO2_CONFIG = 0x12
OK: write reg. OTP_LDO3_VOLT = 0x52
OK: write reg. OTP_LDO3_PWRUP = 0x65
OK: write reg. OTP_LDO3_CONFIG = 0x06
OK: write reg. OTP_LDO4_VOLT = 0x52
OK: write reg. OTP_LDO4_PWRUP = 0x6f
OK: write reg. OTP_LDO4_CONFIG = 0x06
OK: write reg. OTP_VSNVS_CONFIG = 0x00
OK: write reg. OTP_OV_BYPASS1 = 0x7f
OK: write reg. OTP_OV_BYPASS2 = 0x0f
OK: write reg. OTP_UV_BYPASS1 = 0x7f
OK: write reg. OTP_UV_BYPASS2 = 0x0f
OK: write reg. OTP_ILIM_BYPASS1 = 0x7f
OK: write reg. OTP_ILIM_BYPASS2 = 0x0f
OK: write reg. OTP_PROG_IDH = 0x00
OK: write reg. OTP_PROG_IDL = 0x00
OK: write reg. OTP_DEBUG1 = 0x01
OK: write reg. OTP_SW_COMP1 = 0x00
OK: write reg. OTP_SW_COMP2 = 0x00
OK: write reg. OTP_SW_COMP3 = 0x00
OK: write reg. FCMD = 0xa5
OK: write reg. FCMD = 0xa4
OK: write reg. TEST_FLAGS = 0x07
OK: set TBBEN digital pin = LOW
OK: set PWRON digital pin = HIGH

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Please review attached manual for your issue：