Can I adjust the register DDR_SDRAM_INTERVAL of P2020 after the MEM_EN bit of the register DDR_SDRAM_CFG has been setted ?
If it can't be realized, how can I adjust the refresh interval when the DDR controller is working ?
During normal DDR controller operation it is not required to change its registers values, so the controller behaviour is not specified/guaranteed after a register value is changed when MEM_EN=1.
When Tcase of DDR is over 105℃, I need to change the refresh interval, so how to realize?
Use higher refresh rate from the very beginning.
