Routing the DDR Memory Channel To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks Note: The address/command, control, and data groups all have a relationship to the routed clock. Therefore, the effective clock lengths used in the system must satisfy multiple relationships. It is recommended that the designer perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied. Routing DDR3 Data Signals The DDR interface data signals (MDQ[0:63], MDQS[0:8], MDM[0:8], and MECC[0:7]) are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate. An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing (see Table 1). When length-matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the t DQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves: Table 1: Byte Lane to Data Strobe and Data Mask Mapping MDQ[0:7] MDQS0, MDQS0 MDM0 Lane 0 MDQ[8:15] MDQS1, !MDQS1 MDM1 Lane 1 MDQ[16:23] MDQS2, !MDQS2 MDM2 Lane 2 MDQ[24:31] MDQS3, !MDQS3 MDM3 Lane 3 MDQ[32:39] MDQS4, !MDQS4 MDM4 Lane 4 MDQ[40:47] MDQS5, !MDQS5 MDM5 Lane 5 MDQ[48:55] MDQS6, !MDQS6 MDM6 Lane 6 MDQ[56:63] MDQS7, !MDQS7 MDM7 Lane 7 MECC[0:7] MDQS8, !MDQS8 MDM8 Lane 8 DDR Signal Group Layout Recommendations Table 2 lists the layout recommendations for DDR signal groups and the benefit of following each recommendation: Table 2: DDR Signal Groups Layout Recommendations Route each data lane adjacent to a solid ground reference for the entire route to provide the lowest inductance for the return currents Provides the optimal signal integrity of the data interface Note: This concern is especially critical in designs that target the top-end interface speed, because the data switches at 2x the applied clock When the byte lanes are routed, route signals within a byte lane on the same critical layer as they traverse the PCB motherboard to the memories Helps minimize the number of vias per trace and provides uniform signal characteristics for each signal within the data group Alternate the byte lanes on different critical layers Facilitates ease of break-out from the controller perspective, and keeps the signals within the byte group together

For a single eTSEC, I am wiring two external devices via both its parallel interface and SGMII I/F at same time, and either of interfaces actually used will be determined by POR configuration pins. Is this usage possible? Yes. Please ensure that you all the related POR config pins are properly driven.

To enable SD interface in SPI boot on P1025RDB: 1. Perform the following updates in u-boot a) Modify pmuxcr to enable SD bus in case of SPI boot b) Update the corresponding static mux implementation in u-boot 2. Perform the following updates in Linux a) Disable IFC from device tree and kernel defconfig The patch details to enable SD interface are given below. A zip file, AN4336SW.zip, containing the patches for u-boot and Linux accompanies this application note. The file can be downloaded from [1]. U-Boot   Extract the u-boot code from the QorIQ SDK 1.0.1 iso   Apply the patch, u-boot-p1025rdb-enabling-sd-in-spi-boot.patch   Compile the u-boot using "make" command for SPI Flash    make ARCH=powerpc   CROSS_COMPILE=/opt/freescale/usr/local/gcc-4.5.55-eglibc-2.11.55/powerpc-linux-gnu/bin/powerpc-linux-gnu- p1025RDB_SPIFLASH   Use the boot_format utility to generate the spiimage. For more information, see SDK manual.   Update the SPI Flash with the above built spiimage Linux Extract the Linux source code from QorIQ SDK 1.0.1 iso Apply the patch, linux-p1025rdb-enabling-sd-in-spi-boot.patch Compile Linux using make command #make ARCH=powerpc  CROSS_COMPILE=/opt/freescale/usr/local/gcc-4.5.55-eglibc-2.11.55/powerpc-linux-gnu/bin/powerpc-linux-gnuarch/  powerpc/configs/qoriq_sdk_nonsmp_defconfig  #make ARCH=powerpc  CROSS_COMPILE=/opt/freescale/usr/local/gcc-4.5.55-eglibc-2.11.55/powerpc-linux-gnu/bin/powerpc-linux-gnu- Compile the dts ./sripts/dtc/dtc -f -I dts -O dtb -R 8 -S 0x3000  arc/powerpc/boot/dts/p1025rdb.dts.dts > p1025rdb.dtb.dtb With the updated SPI bootloader, Linux uImage and p1025rdb.dtb, the user must be able to enable SD interface on p1025RDB. NOTE The above-mentioned changes must be done only when the user specifically requires the SD interface using SPI boot. For all other boot methods, these patches must not be used.

Can you give detailed information about P1011/20 clock in sources - SYSCLK, DDCCLK and eTSEC_Clock_125? Do these CLOCK source in support Spread Spectrum? What about SD_REF_CLK/SD_REF_CLK#? The spread spectrum parameters table in P1020 HW Spec is valid for SYSCLK and DDRCLK. Spread spectrum clock is not supported for EC_GTX_CLK125 (RGMII). For SERDES, SD_REF_CLK/SD_REF_CLK_B are designed to work with a spread spectrum clock (+0 to –0.5% spreading at 30–33 KHz rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended modulation should be used. Please note that since SGMII doesn't support spread spectrum, if SGMII is used on any SERDES lane, spread spectrum should not be applied to SERDES REF Clock.

When setting the ABSWP bit (in LBCR) in P1020, are the address bytes swapped or just mirrored? Also, can you confirm that the LBCR [ABSWP] affect every device (chip select) being used by the local bus except for the NAND Flash? By setting ABSWP bit (i.e. ABSWP=1), if address=0x12345678. Then LAD [0:15] = 0x7856 and LA[16:31]=0x5678. LBCR [ABSWP] affect every device (chip select) being used by the local bus except for the NAND Flash What is NAND Flash controller speed and size for P1011? AeLBC can work at 83 MHz. At minimum twc, it can be equal to 2 LCLK i.e. half the frequency of LCLK. The maximum page size supported by eLBC is 2K. If I use one mck to drive all 5 ddr3-chips in P1011, can I use the leveling function? Also, which topology do you recommend for this? Yes, writing leveling function should be used to compensate the additional flight time skew delay between different chips introduced by fly-by topology. However, we do not recommend routing the clock in fly-by topology while address, command and control signals routed by other topology. For more detail of JEDEC DDR3 routing topology, please visit [www.JEDEC.org]. Is a 32-bit data interface the only way to control whether or not ABSWP applies (i.e. ABSWP affects 8 and 16-bit data interfaces but does not affect 32-bit data interfaces)? ABSWP also affects 32-bit interface and it is not advisable to set ABSWP for 32 bit interface as only 16 LSB address gets visible on LAD[0:15] and zeroes are output on the LAD[16:31].

For P1020, having a target to achieve the max frequency on local bus what are the requirements on the clock that have to be met? You should pay close attention to the platform clock PLL filtering to minimize jitter. In general keep the bus as short as possible and the trace lengths matched for timing to meet the mentioned Hardware spec requirements.

For P1013/22, what is the maximum bit rate clock for SSI? Is it really 12.285MHz or can it be run up to platform clock / 8? Maximum bit rate clock for SSI is as per hardware spec i.e. 12.285MHz. This is the maximum speed at which the SSI IP is guaranteed to work. From a system perspective it is possible to clock it at a higher speed, but for P1013 that is not supported. If platform clock is 400MHz, please use appropriate values of DIV2, PSR and PM to ensure that the bit rate clock for SSI does not exceed 12.285MHz. Can you please confirm that the P1022 ethernet input clock is actually 2 clocks: one for each eTSEC, with name TSECn_GTX_CLK125/GPIOm? The p1022 ballmap spreadsheet only shows one gtx_clk125 pin (like the 8536), but the current data sheet (Revision E) indicates there are two. The ball map shows only primary functions of a pin. By default both the eTSECs would share the same clock i.e TSEC1_GTX_CLK125 @Y29. If required, user can opt to use separate clock for eTSEC2 . The separate clock for eTSEC2 is multiplexed with TSEC_1588_TRIG_IN1@AH27 and can be configured using PMUXCR[6:7]. The SD card spec requires SD clock to supply for at least 74 clock cycles. On the other hand, the eSDHC controller in P1022 supplies about 13 SD clock cycles (with 180 degrees phase shift) at power up. Will SD card have any reliability issue by this fewer clock cycles than what is required by spec? No, SD card should not have the reliability issue. 74 clocks can be supplied by setting SYSCTL [INITA]. The 180 degree phase shift will not affect card or eSDHC IP block's operation. The phase shift is due to the synchronizer.

Routing the DDR Memory Channel To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks Note: The address/command, control, and data groups all have a relationship to the routed clock. Therefore, the effective clock lengths used in the system must satisfy multiple relationships. It is recommended that the designer perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied. Routing DDR3 Data Signals The DDR interface data signals (MDQ[0:63], MDQS[0:8], MDM[0:8], and MECC[0:7]) are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate. An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing (see Table 1). When length-matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the t DQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves: Table 1: Byte Lane to Data Strobe and Data Mask Mapping Data Data Strobe Data Mask Lane Number MDQ[0:7] MDQS0, MDQS0 MDM0 Lane 0 MDQ[8:15] MDQS1, !MDQS1 MDM1 Lane 1 MDQ[16:23] MDQS2, !MDQS2 MDM2 Lane 2 MDQ[24:31] MDQS3, !MDQS3 MDM3 Lane 3 MDQ[32:39] MDQS4, !MDQS4 MDM4 Lane 4 MDQ[40:47] MDQS5, !MDQS5 MDM5 Lane 5 MDQ[48:55] MDQS6, !MDQS6 MDM6 Lane 6 MDQ[56:63] MDQS7, !MDQS7 MDM7 Lane 7 MECC[0:7] MDQS8, !MDQS8 MDM8 Lane 8 DDR Signal Group Layout Recommendations Table 2 lists the layout recommendations for DDR signal groups and the benefit of following each recommendation: Table 2: DDR Signal Groups Layout Recommendations Recommendation Benefit Route each data lane adjacent to a solid ground reference for the entire route to provide the lowest inductance for the return currents Provides the optimal signal integrity of the data interface Note: This concern is especially critical in designs that target the top-end interface speed, because the data switches at 2x the applied clock When the byte lanes are routed, route signals within a byte lane on the same critical layer as they traverse the PCB motherboard to the memories Helps minimize the number of vias per trace and provides uniform signal characteristics for each signal within the data group Alternate the byte lanes on different critical layers Facilitates ease of break-out from the controller perspective, and keeps the signals within the byte group together

The on-chip ROM code does not set up any local access windows (LAWs). Access to the CCSR address space or the L2 cache does not require a LAW. It is the user’s responsibility to set up a LAW through a control word address/data pair for the desired target address and execution starting address (which is typically in either DDR or local bus memory space). Required Configurations for SD Card/MMC Booting The configuration settings required to boot from an SD card/MMC are as follows: Ensure that cfg_rom_loc[0:3] (Boot_Rom_Loc) are driven with a value of 0b0111. Only one core can be in booting mode. If your device has multiple cores, all other cores must be in a boot hold-off mode. The CPU boot configuration input, cfg_cpux_boot, should be 0, where x is from 1 to n (n = the number of cores). Booting from the eSDHC interface can occur from different SD card slots if multiple SD card slots are designed on the board. In this case, ensure the appropriate SD card/MMC is selected For example, on the P1021 board, bit 7 of the SW8 is used to select which SD/MMC slot is used. If SW8[7] = 1, an SD card/MMC must be put to the external SD card/MMC slot (J1). TIP The polarity of the SDHC_CD signal should be active-low.  Required Configurations for EEPROM Booting The configuration settings required to boot from an EEPROM are as follows: Ensure that cfg_rom_loc[0:3] (Boot_Rom_Loc) are driven with a value of 0b0110. Only one core can be in booting mode. If your device has multiple cores, all other cores must be in a boot hold-off mode. The CPU boot configuration input, cfg_cpux_boot, should be 0, where x is from 1 to n (n = the number of cores). The eSPI chip select 0 (SPI_CS[0]) must be connected to the EEPROM that is used for booting. No other chip select can be used for booting. This is because during booting, the eSPI controller is configured to operate in master mode. Booting from the eSPI interface only works with SPI_CS[0].

As P1025RM.pdf shows, one can multiplex some pins such as, LAD8/GE_PA0 multiplexing. My design uses LOCAL BUS (nor flash) and UTOPIA at the same time. Can I design my product like this in view of pin multiplexing? LAD8 must be used as local bus pin. For UTOPIA, this pin serves as PA0, which is UTOPIA TX address 4. Usually this UTOPIA signal can be not-used. P1025 Reference Manual chapter 12.5.1.2 states that LAD [0:15] can carry both A [0:15] and A [16:31] via ABSWAP setting switching. How can I use it to skip LAD8 to address local bus device? ABSWAP is not used dynamically. It should be set either 0 or 1 but not be switched from time to time. In this case only A [16:31] (from LAD) is available when ABSWAP is used (set to 1). In this case this can only be used if customer requires 16 bit or fewer address lines. In P1025/P1016, for UTOPIA pins UPC1_RxADDR [2:4]/UPC1_TxADDR [2:4], each signal has two pins described in p1025RM. Based on this, can I use any one of the pins LAD08 or MDVAL for UPC1_TxADDR [4]? For LAD08, I'll assign this pin for LOCAL BUS. Yes, you can use any one of the 2 pins for these signals using PMUXCR register. UPC1_TxADDR [4] can be either the one multiplexed with LAD08 or MDVAL. You can assign LAD08 pin for LOCAL BUS. Also remind you that, UPC1_TxADDR 4] is MSB, if only 4-bit UTOPIA address is needed, just use UPC1_TxADDR [0:3] and this LAD08/UPC1_TxADDR[4] pin can be configured as LAD08 by clearing PMUXCR[QE1] bit to 0. In P1025/P1016, I saw that LOE/ LGPL2/ LFRE in the same line, but in P1016EC.pdf, only LGPL2 is present in B14-pin description and I cannot find LOE/LFRE. Can LOE/LFRE (GPCM read enable) signal use B14-pin? LOE/LFRE (GPCM read enable) signal can use B14-pin. For LGPLx pins, we only put the LPGLx in our hardware spec. You can find all other multiplexed function from P1025/P1016 reference manual.

Should I tie "UART_RTS_B01" to "0" while configuring signals sampled at reset in P1011? If eTSEC1 is required in RGMII mode then the POR configuration pins should be set to {EC_MDC,TSEC1_TXD0,TSEC1_TXD7} = {010} and if eTSEC3 is required in RGMII mode then {UART_RTS0,UART_RTS1,TSEC_1588_ALARM_OUT2} = {101} As all above signals default POR value is 1, you have to specify the signals that should be externally pull-down through a resistor when ever logic zero is required

Product Information on Freescale.com P1010 Product Summary Page P1010 Documentation P1010 Software and Tools P1010 Parametrics P1010 Training Frequently Asked Questions (FAQ) P1010/P1014 USB Specific FAQs   P1010/P1014 Ethernet (eTSEC) Specific FAQs   P1010/P1014 DDR Specific FAQs   Tips and Tricks Enabling SD Interface on P1010 Reference Design Board   Hardware and Design Layout/Guidelines for P1010 DDR3 SRAM Interfaces   Other Resources CodeWarrior for Power Architecture Processors Optimizing CodeWarrior on Power Architecture Tips for your brand new CodeWarrior TAP! (Power Architecture)

The on-chip ROM code does not set up any local access windows (LAWs). Access to the CCSR address space or the L2 cache does not require a LAW. It is the user’s responsibility to set up a LAW through a control word address/data pair for the desired target address and execution starting address (which is typically in either DDR or local bus memory space).   Required Configurations for SD Card/MMC Booting The configuration settings required to boot from an SD card/MMC are as follows: Ensure that cfg_rom_loc[0:3] (Boot_Rom_Loc) are driven with a value of 0b0111. Only one core can be in booting mode. If your device has multiple cores, all other cores must be in a boot hold-off mode. The CPU boot configuration input, cfg_cpux_boot, should be 0, where x is from 1 to n (n = the number of cores). Booting from the eSDHC interface can occur from different SD card slots if multiple SD card slots are designed on the board. In this case, ensure the appropriate SD card/MMC is selected For example, on the P1022 board, bit 7 of the SW8 is used to select which SD/MMC slot is used. If SW8[7] = 1, an SD card/MMC must be put to the external SD card/MMC slot (J1). TIP The polarity of the SDHC_CD signal should be active-low.   Required Configurations for EEPROM Booting The configuration settings required to boot from an EEPROM are as follows: Ensure that cfg_rom_loc[0:3] (Boot_Rom_Loc) are driven with a value of 0b0110. Only one core can be in booting mode. If your device has multiple cores, all other cores must be in a boot hold-off mode. The CPU boot configuration input, cfg_cpux_boot, should be 0, where x is from 1 to n (n = the number of cores). The eSPI chip select 0 (SPI_CS[0]) must be connected to the EEPROM that is used for booting. No other chip select can be used for booting. This is because during booting, the eSPI controller is configured to operate in master mode. Booting from the eSPI interface only works with SPI_CS[0].  

Table of Contents Product Information on Freescale.com P1020 Product Summary Page P1020 Documentation P1020 Software and Tools P1020 Parametrics P1020 Training Frequently Asked Questions (FAQ) P1020/P1011 Clocking Specific FAQs P1020/P1011 COP/JTAG Specific FAQs P1020/P1011 Ethernet (eTSEC) Specific FAQs P1020/P1011 Hardware Specifications/Reference Manual Specific FAQs P1020/P1011 IBIS Specific FAQs P1020/P1011 Local Bus Specific FAQs P1020/P1011 Memory Controller Specific FAQs P1020/P1011 Reset Configuration Specific FAQs P1020/P1011 SPI Specific FAQs Tips & Tricks Booting P1020/P1011 from On-Chip ROM (eSDHC or eSPI) Booting to Linux from an SD Card/MMC for P1020/P1011 Getting Started Getting Started Guide for P1020/P1011 Discussions P1020 Processor QorIQ P1 Devices Other Resources CodeWarrior for Power Architecture Processors Optimizing CodeWarrior on Power Architecture Tips for your brand new CodeWarrior TAP! (Power Architecture)

For P1013/P1022, when I am using a DDR controller with a 64-bit interface with a 32-bit memory sub system, which lanes should I use? When a 64-bit DDR interface is configured in a 32-bit data bus width, lanes [0:3] (MDQ [0:31]) will be used.

Usually, when I turn on the option of "reset target on launch" CW resets CPU again while connecting to CPU. With P1015, CodeWarrior (CW) does not connect to CPU when the option is on, only when I disable the option, CW can connect to CPU. What could be the problem? . "Reset target on launch" asserts HRESET to the target, thereby resetting the hardware. In most cases this is a required step, but where you don't want to assert HRESET or where your Target Initialization (.cfg) file does this for you with the "reset 1" command, you can do without this option enabled. "P10xx-P20xxRDB_P1011_jtag.txt" JTAG Configuration file is required by 8.8 CW PA for all single-core P10xx processors. Please load the “P20xxRDB_P1011_jtag.txt" JTAG Configuration file in your USB TAP configuration panel you mentioned about. 1) Set MACCFG1[Rx_Flow] && MACCFG1[Tx_Flow] to 1 2) Set RCTRL[LFC] to 1.

Routing the DDR Memory Channel To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks Note: The address/command, control, and data groups all have a relationship to the routed clock. Therefore, the effective clock lengths used in the system must satisfy multiple relationships. It is recommended that the designer perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied. Routing DDR3 Data Signals The DDR interface data signals (MDQ[0:63], MDQS[0:8], MDM[0:8], and MECC[0:7]) are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate. An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing (see Table 1). When length-matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the t DQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves: Table 1: Byte Lane to Data Strobe and Data Mask Mapping Data Data Strobe Data Mask Lane Number MDQ[0:7] MDQS0, MDQS0 MDM0 Lane 0 MDQ[8:15] MDQS1, !MDQS1 MDM1 Lane 1 MDQ[16:23] MDQS2, !MDQS2 MDM2 Lane 2 MDQ[24:31] MDQS3, !MDQS3 MDM3 Lane 3 MDQ[32:39] MDQS4, !MDQS4 MDM4 Lane 4 MDQ[40:47] MDQS5, !MDQS5 MDM5 Lane 5 MDQ[48:55] MDQS6, !MDQS6 MDM6 Lane 6 MDQ[56:63] MDQS7, !MDQS7 MDM7 Lane 7 MECC[0:7] MDQS8, !MDQS8 MDM8 Lane 8 DDR Signal Group Layout Recommendations Table 2 lists the layout recommendations for DDR signal groups and the benefit of following each recommendation: Table 2: DDR Signal Groups Layout Recommendations Recommendation Benefit Route each data lane adjacent to a solid ground reference for the entire route to provide the lowest inductance for the return currents Provides the optimal signal integrity of the data interface Note: This concern is especially critical in designs that target the top-end interface speed, because the data switches at 2x the applied clock When the byte lanes are routed, route signals within a byte lane on the same critical layer as they traverse the PCB motherboard to the memories Helps minimize the number of vias per trace and provides uniform signal characteristics for each signal within the data group Alternate the byte lanes on different critical layers Facilitates ease of break-out from the controller perspective, and keeps the signals within the byte group together

For P1015, does DDRCLK and PCIe (SerDes) ref clock support a spread spectrum reference? DDRCLK and PCIe (SerDes) ref clock support spread spectrum. Please note that since SGMII doesn't support spread spectrum, if SGMII is used on any SERDES lane, spread spectrum should not be applied to SERDES REF clock. What are the DDRCLK and PCIe (SerDes) reference clock spread spectrum parameters for P1015?  DDRCLK and PCIe (SerDes) reference clock are designed to work with a spread spectrum clock (+0 to –0.5% spreading at 30–33 KHz rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended modulation should be used.

Please confirm that a PCIe lane on the P1023 can be enabled after POR (configured off in h/w but turned on in s/w). If so how this would be implemented? It is possible to control PCIe Lane turned on through s/w. You can control this through SRDSCR2 [0:7]. Through this control you can power -up or power- down individual lanes separately What is the difference between two strap options for PCIe ports - 0b00 or 0b11? In terms of PCIe, options 0b00 and 0b11 are redundant, but in terms of SGMII, they are different 0b00 - 2 lanes are for PCIe; the remaining 2 lanes are powered down 0b11 - 2 lanes are for PCIe; the remaining 2 lanes are for SGMII 0b01 - 3 lanes are for PCIe; the remaining 1 lane is powered down 0b10 - 3 lanes are for PCIe; the remaining 1 lane is for SGMII When SGMII is not used, the corresponding lane(s) should be powered down to save power.

Routing the DDR Memory Channel To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks Note: The address/command, control, and data groups all have a relationship to the routed clock. Therefore, the effective clock lengths used in the system must satisfy multiple relationships. It is recommended that the designer perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied. Routing DDR3 Data Signals The DDR interface data signals (MDQ[0:63], MDQS[0:8], MDM[0:8], and MECC[0:7]) are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate. An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing (see Table 1). When length-matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the t DQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves: Table 1: Byte Lane to Data Strobe and Data Mask Mapping Data Data Strobe Data Mask Lane Number MDQ[0:7] MDQS0, MDQS0 MDM0 Lane 0 MDQ[8:15] MDQS1, !MDQS1 MDM1 Lane 1 MDQ[16:23] MDQS2, !MDQS2 MDM2 Lane 2 MDQ[24:31] MDQS3, !MDQS3 MDM3 Lane 3 MDQ[32:39] MDQS4, !MDQS4 MDM4 Lane 4 MDQ[40:47] MDQS5, !MDQS5 MDM5 Lane 5 MDQ[48:55] MDQS6, !MDQS6 MDM6 Lane 6 MDQ[56:63] MDQS7, !MDQS7 MDM7 Lane 7 MECC[0:7] MDQS8, !MDQS8 MDM8 Lane 8 DDR Signal Group Layout Recommendations Table 2 lists the layout recommendations for DDR signal groups and the benefit of following each recommendation: Table 2: DDR Signal Groups Layout Recommendations Recommendation Benefit Route each data lane adjacent to a solid ground reference for the entire route to provide the lowest inductance for the return currents Provides the optimal signal integrity of the data interface Note: This concern is especially critical in designs that target the top-end interface speed, because the data switches at 2x the applied clock When the byte lanes are routed, route signals within a byte lane on the same critical layer as they traverse the PCB motherboard to the memories Helps minimize the number of vias per trace and provides uniform signal characteristics for each signal within the data group Alternate the byte lanes on different critical layers Facilitates ease of break-out from the controller perspective, and keeps the signals within the byte group together