These values are worse than those specified in the datasheet.
1.
To achieve the target values, the reference clock with low phase noise must be used. The requirements are listed in the TFF1003HN datasheet Table 10. You can find more about this topic in this user guide:
Example design to generate CW ref. signal for TFF1xxxx
https://www.nxp.com/docs/en/user-guide/UM_TFF1xxxx_cleanupPLL_V2.0.pdf
2.
Any noise/ripple on the supply might convert to excessive phase noise/jitter. For this reason it is very important to implement a clean noise and ripple free supply for reference clock circuit and PLL blocks.
3.
OM17004 demo board can be requested through distributors.
https://eu.mouser.com/ProductDetail/NXP-Semiconductors/OM17004-TFF1003?qs=fAHHVMwC%252BbgHalvoHHUXMA...
Have a great day,
Pavel
NXP TIC
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